发明公开
EP0498201A2 Generic high bandwidth adapter architecture
失效
Architektur im Allgemeinen von Adapter mit einer hohen Bandbreite。
- 专利标题: Generic high bandwidth adapter architecture
- 专利标题(中): Architektur im Allgemeinen von Adapter mit einer hohen Bandbreite。
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申请号: EP92100855.3申请日: 1992-01-20
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公开(公告)号: EP0498201A2公开(公告)日: 1992-08-12
- 发明人: Chang, Paul , Delp, Gary Scott , Meleis, Hanafy El-Sayed , Montalvo, Rafael Mantilla , Seidman, David Israel , Tantawy, Ahmed Nasr-El-Din , Zumbo, Dominick Anthony
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Jost, Ottokarl, Dipl.-Ing.
- 优先权: US651894 19910206
- 主分类号: G06F13/38
- IPC分类号: G06F13/38 ; G06F13/40
摘要:
A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.
公开/授权文献
- EP0498201A3 Generic high bandwidth adapter architecture 公开/授权日:1996-09-11
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