公开(公告)号：EP0498201A2

公开(公告)日：1992-08-12

申请号：EP92100855.3

申请日：1992-01-20

申请人： International Business Machines Corporation

发明人： Chang, Paul ,  Delp, Gary Scott ,  Meleis, Hanafy El-Sayed ,  Montalvo, Rafael Mantilla ,  Seidman, David Israel ,  Tantawy, Ahmed Nasr-El-Din ,  Zumbo, Dominick Anthony

IPC分类号： G06F13/38 ,  G06F13/40

CPC分类号： H04L49/9026 ,  G06F5/06 ,  G06F13/128 ,  G06F13/387 ,  H04L12/18 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

摘要翻译： 通用高带宽适配器，为总线，通道，处理器，交换结构和/或通信网络之间的数据通信提供统一架构。 数据由可变长度的数据流分组携带，每个分组包括用于中介信息交换的通信协议所需的报头控制信息部分，通常是要传送的数据的数据部分。 通用高带宽适配器包括处理器子系统，其包括用于处理数据分组的报头控制信息部分的处理器。 处理器可以访问存储在分组存储器中的数据分组，其存储到达四个通用适配器输入/输出端口的数据分组。 分组存储器被分割成多个缓冲器，并且每个数据分组根据其长度的要求存储在一个或多个缓冲器中。 提供通用适配器管理器用于执行和同步通用适配器管理功能，包括通过在缓冲器中组织数据分组来实现分组存储器中的数据结构，以及将数据分组组织成队列以供处理器子系统处理或从通用适配器输入传输 /输出端口。 每个通用适配器输入/输出端口具有与其相关联的分组存储器接口，用于将数据分组传入和传出分组存储器，使得当在输入/输出端口处接收到数据分组时，数据分组被传送到 适配器包内存并排队处理。

公开(公告)号：EP0498201A3

公开(公告)日：1996-09-11

申请号：EP92100855.3

申请日：1992-01-20

申请人： International Business Machines Corporation

发明人： Chang, Paul ,  Delp, Gary Scott ,  Meleis, Hanafy El-Sayed ,  Montalvo, Rafael Mantilla ,  Seidman, David Israel ,  Tantawy, Ahmed Nasr-El-Din ,  Zumbo, Dominick Anthony

IPC分类号： G06F13/38 ,  G06F13/40

CPC分类号： H04L49/9026 ,  G06F5/06 ,  G06F13/128 ,  G06F13/387 ,  H04L12/18 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.