发明授权
EP0547240B1 RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE
失效
具有快速中断或异常模式RISC微处理器架构
- 专利标题： RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE
- 专利标题（中）： 具有快速中断或异常模式RISC微处理器架构
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申请号： EP92914386.5申请日： 1992-07-07
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公开(公告)号： EP0547240B1公开(公告)日： 2000-01-12
- 发明人: NGUYEN, Le Trong , LENTZ, Derek, J. , MIYAYAMA, Yoshiyuki , GARG, Sanjiv , HAGIWARA, Yasuaki , WANG, Johannes , TRANG, Quang, H.
- 申请人： SEIKO EPSON CORPORATION
- 申请人地址： 4-1, Nishishinjuku 2-chome Shinjuku-ku, Tokyo 163-0811 JP
- 专利权人： SEIKO EPSON CORPORATION
- 当前专利权人： SEIKO EPSON CORPORATION
- 当前专利权人地址： 4-1, Nishishinjuku 2-chome Shinjuku-ku, Tokyo 163-0811 JP
- 代理机构： Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
- 优先权： US726942 19910708
- 国际公布： WO9301547 19930121
- 主分类号： G06F9/38
- IPC分类号： G06F9/38
摘要：
Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
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