公开(公告)号：EP0547241B1

公开(公告)日：2001-10-10

申请号：EP92914387.3

申请日：1992-07-07

申请人： SEIKO EPSON CORPORATION

发明人： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  LAU, Tei-Li ,  TRANG, Quang, H.

IPC分类号： G06F9/38

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions.

公开(公告)号：EP0638183B1

公开(公告)日：1997-03-05

申请号：EP93909433.0

申请日：1993-04-27

申请人： SEIKO EPSON CORPORATION

发明人： WANG, Johannes ,  GARG, Sanjiv ,  DEOSARAN, Trevor

IPC分类号： G06F9/38

CPC分类号： G06F9/3012 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3885

摘要： A system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

公开(公告)号：EP0677188B1

公开(公告)日：1996-10-09

申请号：EP94904480.4

申请日：1993-12-16

申请人： SEIKO EPSON CORPORATION

发明人： IADONATO, Kevin, R. ,  DEOSARAN, Trevor, A. ,  GARG, Sanjiv

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3885

摘要： Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.

公开(公告)号：EP0682789B1

公开(公告)日：1998-09-09

申请号：EP94904479.6

申请日：1993-12-16

申请人： SEIKO EPSON CORPORATION

发明人： DEOSARAN, Trevor A. ,  GARG, Sanjiv ,  IADONATO, Kevin R.

IPC分类号： G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

公开(公告)号：EP0682789A1

公开(公告)日：1995-11-22

申请号：EP94904479.0

申请日：1993-12-16

申请人： SEIKO EPSON CORPORATION

发明人： DEOSARAN, Trevor A. ,  GARG, Sanjiv ,  IADONATO, Kevin R.

IPC分类号： G06F9

CPC分类号： G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

公开(公告)号：EP0677188A1

公开(公告)日：1995-10-18

申请号：EP94904480.0

申请日：1993-12-16

申请人： SEIKO EPSON CORPORATION

发明人： IADONATO, Kevin, R. ,  DEOSARAN, Trevor, A. ,  GARG, Sanjiv

IPC分类号： G06F9

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3885

摘要： Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.

公开(公告)号：EP0636256A1

公开(公告)日：1995-02-01

申请号：EP93906834.0

申请日：1993-03-26

申请人： SEIKO EPSON CORPORATION

发明人： GARG, Sanjiv ,  IADONATO, Kevin, Ray

IPC分类号： G06F9 ,  G06F15

CPC分类号： G06F9/3013 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

公开(公告)号：EP0547248A1

公开(公告)日：1993-06-23

申请号：EP92914445.0

申请日：1992-07-07

申请人： SEIKO EPSON CORPORATION

发明人： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  TRANG, Quang, H. ,  LAU, Te-Li

IPC分类号： G06F9 ,  G06F12 ,  G06F15

CPC分类号： G06F9/30043 ,  G06F9/30029 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/327 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3814 ,  G06F15/7842

摘要： Technique de conception de microprocesseur selon laquelle les principaux modules fonctionnels d'une architecture de microprocesseur sont divisés en une partie d'extrémité avant et une partie d'extrémité arrière. La partie d'extrémité arrière, qui assure l'interface entre la partie d'extrémité avant et la mémoire, est commune à deux ou plusieurs conceptions de microprocesseur, et la partie d'extrémité avant, qui comprend tous les moyens d'interprétation et d'exécution des instructions, est différente pour chacun des différents microprocesseurs.

公开(公告)号：EP0547240A1

公开(公告)日：1993-06-23

申请号：EP92914386.0

申请日：1992-07-07

申请人： SEIKO EPSON CORPORATION

发明人： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  TRANG, Quang, H.

IPC分类号： G06F9 ,  G06F15

CPC分类号： G06F9/3865 ,  G06F9/3017 ,  G06F9/32 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4812 ,  G06F15/7842

摘要： Mécanisme d'interruption rapide pour microprocesseur, selon lequel est entretenue une table d'interruption de vecteur comportant un espace pour diverses instructions dans chaque entrée de table. Lorsqu'une interruption rapide se produit, la commande est transférée directement dans l'entrée de table correspondant au numéro d'interruption. Le sous-programme de gestion d'interruption peut être installé complètement à l'intérieur de l'entrée de table, ou il peut transférer la commande à un code de sous-programme de gestion complémentaire.

公开(公告)号：EP0547247B1

公开(公告)日：2001-04-04

申请号：EP92914444.2

申请日：1992-07-07

申请人： SEIKO EPSON CORPORATION

发明人： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  LAU, Tei-Li ,  TRANG, Quang, H.

IPC分类号： G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.