发明公开
EP0568818A2 Semiconductor memory device and operational method with reduced well noise
失效
Halbleiterspeicheranordnung und Getriebeverfahren mit verminderter Wannenrausch。
- 专利标题: Semiconductor memory device and operational method with reduced well noise
- 专利标题(中): Halbleiterspeicheranordnung und Getriebeverfahren mit verminderter Wannenrausch。
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申请号: EP93105501.6申请日: 1993-04-02
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公开(公告)号: EP0568818A2公开(公告)日: 1993-11-10
- 发明人: Bronner, Gary Bela , Dhong, Sang Hoo
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Schäfer, Wolfgang, Dipl.-Ing.
- 优先权: US879822 19920507
- 主分类号: G11C11/407
- IPC分类号: G11C11/407 ; G11C5/14
摘要:
A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.
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