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EP0568818A2 Semiconductor memory device and operational method with reduced well noise 失效
Halbleiterspeicheranordnung und Getriebeverfahren mit verminderter Wannenrausch。

Semiconductor memory device and operational method with reduced well noise
摘要:
A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.
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