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    Providing dual work function doping
    4.
    发明公开
    Providing dual work function doping 审中-公开
    Dotierung zur Erzielung einer doppelten Austrittsarbeit

    公开(公告)号：EP0929101A1

    公开(公告)日：1999-07-14

    申请号：EP98310525.5

    申请日：1998-12-21

    申请人： International Business Machines Corporation

    发明人： Bronner, Gary Bela ,  Gambino, Jeffrey P. ,  Mandelman, Jack A. ,  Radens, Carl J. ,  Tonti, William Robert

    IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/28 ,  H01L21/225

    CPC分类号： H01L21/28035 ,  H01L21/82345

    摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

    摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选择数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些栅极结构，从而提供双功能掺杂 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，由此各个栅极结构在其顶部部分包含自对准绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。

    Non-random sub-lithography vertical stack capacitor
    5.
    发明公开
    Non-random sub-lithography vertical stack capacitor 失效
    Nicht-wahlfreier sublithographischer vertikaler Stapelkondensator

    公开(公告)号：EP0696052A2

    公开(公告)日：1996-02-07

    申请号：EP95480080.1

    申请日：1995-06-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chen, Bomy Able ,  Nguyen, Son van ,  Bronner, Gary Bela

    IPC分类号： H01L21/3205 ,  H01L21/033 ,  H01L21/8242

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  Y10S438/947

    摘要： Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. Large polysilicon blocks or plugs (38) are formed onto a conventional interconnect structure for accessing a memory cell prior to forming a capacitor which can extend over a portion of a bit line and the insulating cap and sidewalls. This is preferably done by providing a thick polysilicon deposition in a blanket layer by any known process. This blanket layer is then preferably planarized and then etched to separate the layer into blocks or plugs which are in contact with the conductive studs connected to transistors. Deep grooves are formed in the polysilicon plug (38). The polysilicon plug is surrounded with TEOS oxide and includes concentric rings which are of sustantial mechanical integrity, particularly after a oxide-nitride-oxide (ONO) layer (60) of about 5 nm thickness is conformally deposited in the grooves and the remainder of the grooves are filled with a conductor (62) such as aluminium or polysilicon to complete the other capacitor plate. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.

    摘要翻译： 亚光刻尺寸的集成电路结构通过在待蚀刻材料体上的孔内的不同蚀刻速率的交替层材料的共形沉积形成。 然后选择性地和优先地蚀刻交替层中的一种材料以形成掩模，通过该掩模可以对要蚀刻的材料的主体进行蚀刻。 在形成电容器之前，将大多晶硅块或插头（38）形成在常规的互连结构上，用于访问存储器单元，该电容器可以在位线的一部分和绝缘盖和侧壁上延伸。 优选通过任何已知方法在覆盖层中提供厚的多晶硅沉积来完成。 然后优选将该覆盖层平面化，然后蚀刻以将该层分离成与连接到晶体管的导电柱相接触的块或插塞。 在多晶硅塞（38）中形成有深沟槽。 多晶硅插塞被TEOS氧化物包围，并且包括具有维持机械完整性的同心环，特别是在约5nm厚度的氧化物 - 氮化物 - 氧化物（ON））层（60）共形沉积在凹槽中并且其余部分 沟槽填充有诸如铝或多晶硅的导体（62），以完成另一个电容器板。 该技术特别适用于形成用于存储器单元的结构稳健的电容器，其大大增加了板面积，导致增加的电容，同时保持电容器结构的小的占地面积。

    Semiconductor memory device and operational method with reduced well noise
    6.
    发明公开
    Semiconductor memory device and operational method with reduced well noise 失效
    具有减少噪声的半导体存储器件和操作方法

    公开(公告)号：EP0568818A3

    公开(公告)日：1994-08-10

    申请号：EP93105501.6

    申请日：1993-04-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo

    IPC分类号： G11C11/407 ,  G11C5/14

    CPC分类号： G11C5/146

    摘要： A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.

    Method for dual gate oxide dual workfunction CMOS
    7.
    发明公开
    Method for dual gate oxide dual workfunction CMOS 审中-公开
    Verfahrenfüreinen CMOS mit zweifachem Gateoxid und zweifacher Austrittsarbeit

    公开(公告)号：EP0935285A1

    公开(公告)日：1999-08-11

    申请号：EP99300234.4

    申请日：1999-01-14

    申请人： International Business Machines Corporation

    发明人： Bronner, Gary Bela ,  El-Kareh, Badih ,  Schuster, Stanley Everett

    IPC分类号： H01L21/8239 ,  H01L21/8238

    CPC分类号： H01L27/10873 ,  H01L21/823842

    摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

    摘要翻译： 在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚的和薄的栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，逻辑电路可以由同一芯片上的薄氧化物FET构成。 首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。 堆叠包括在栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。 选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。 在再曝光的晶片上形成更薄的栅氧化层。 接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。 在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。 最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

    Semiconductor memory device and operational method with reduced well noise
    8.
    发明公开
    Semiconductor memory device and operational method with reduced well noise 失效
    Halbleiterspeicheranordnung und Getriebeverfahren mit verminderter Wannenrausch。

    公开(公告)号：EP0568818A2

    公开(公告)日：1993-11-10

    申请号：EP93105501.6

    申请日：1993-04-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo

    IPC分类号： G11C11/407 ,  G11C5/14

    CPC分类号： G11C5/146

    摘要： A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.

    摘要翻译： 提供了具有降低的井噪声的半导体存储器件和操作方法。 存储器件包括多个存储单元，其以阵列阵列内的行和列排列并且可由多个字线和位线寻址。 阵列阱被偏置到期望的电位，并且采用读出放大器来在预定位线信号显影周期期间读取位线状态。 在该信号显影的至少一部分期间去除阵列阱偏置，使得当位线上正在开发信号时，阱电位漂浮（理想地保持稳定）。 这种临时浮动井技术对开放式位线架构尤为重要。

    Trench DRAM cell array
    9.
    发明公开
    Trench DRAM cell array 失效
    沟槽DRAM单元阵列

    公开(公告)号：EP0550894A1

    公开(公告)日：1993-07-14

    申请号：EP92122009.1

    申请日：1992-12-24

    申请人： International Business Machines Corporation

    发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo ,  Hwang, Wei ,  Park, Jong Woo ,  Voldman, Steven Howard

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10829

    摘要： A high density substrate plate trench DRAM cell memory device and process are described in which a buried region (32) is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate (10). The buried region (32) is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches (22). The buried region (32) is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

    摘要翻译： 描述了一种高密度衬底板沟槽DRAM单元存储器件和工艺，其中掩埋区域（32）与深沟槽电容器相邻形成，使得DRAM传输FET的衬底区域可以与半导体衬底上的其他FET电隔离 10）。 掩埋区域（32）通过离子注入和扩散部分地形成以与深沟槽（22）的壁相交。 掩埋区域（32）沿其周边与达到的区域接触以完成隔离。 由于更好地控制器件寄生效应，组合区域减少了电荷损失。