A general massively parallel computer architecture supporting neural networks is developed utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip, that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. A partitioning approach is presented first, where for a given size K and X, and K is divisible by X, it is proven that a triangular array containing K processor elements located on each edge of an equilateral triangular array can be partitioned into K/X triangular arrays of dimension X and K(K-X) / 2X ² square processor arrays of dimension X. An algorithm is presented next which partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable massively parallel computing structure for N root tree processors utilizes N ²/ X ² triangular processor group chips. Examples of using the partitioning methodology to create the scalable organization of processor elements are presented. Following these examples, an interconnection mechanism is developed which is shown to preserve the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X. Examples of the interconnection mechanism for two scaled neural network emulation massively parallel computers utilizing the same size X processor group chip are presented. Finally, an alternative scaling mechanism and implementation considerations for the interconnection mechanisms are discussed.