公开(公告)号：EP0569764A2

公开(公告)日：1993-11-18

申请号：EP93106731.8

申请日：1993-04-26

申请人： International Business Machines Corporation

发明人： Pechanek, Gerald G. ,  Vassiliadis, Stamatis ,  Delgadofrias, Jose Guadelupe

IPC分类号： G06F15/80

CPC分类号： G06N3/10 ,  G06F15/8023 ,  G06N3/063

摘要： A general massively parallel computer architecture supporting neural networks is developed utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip, that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. A partitioning approach is presented first, where for a given size K and X, and K is divisible by X, it is proven that a triangular array containing K processor elements located on each edge of an equilateral triangular array can be partitioned into K/X triangular arrays of dimension X and K(K-X) / 2X ² square processor arrays of dimension X. An algorithm is presented next which partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable massively parallel computing structure for N root tree processors utilizes N ²/ X ² triangular processor group chips. Examples of using the partitioning methodology to create the scalable organization of processor elements are presented. Following these examples, an interconnection mechanism is developed which is shown to preserve the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X. Examples of the interconnection mechanism for two scaled neural network emulation massively parallel computers utilizing the same size X processor group chip are presented. Finally, an alternative scaling mechanism and implementation considerations for the interconnection mechanisms are discussed.

摘要翻译： 一般大规模并行计算机体系结构支持神经网络被开发利用分离三角形阵列包含在每个边缘上N个处理元件为多个较小的三角阵列，每一维X的的新方法，并且每个代表一个通用构建块处理器组芯片，确实可以 进行互连的各种尺寸的并行处理实现。 组芯片通过独特的开关树机构相互连接做了维护在由尺寸为N的原始三角形阵列的分隔方法是第一次提出，其中对于给定尺寸K和X，以及K是整除具有的完整的连接能力和功能 X，它被证明没有三角形阵列包含位于等边三角形阵列的每个边缘K处理器元件可以被划分成尺寸X和K（KX）的K / X三角阵列/ 2X <2>尺寸X的平方处理器阵列 。提出的算法下哪些分区的正方形阵列分成两个三角阵列，每一维X.假设K = N和所选择的技术的支持三角形处理器芯片组尺寸X的在单个芯片上的位置，最终可扩展的大规模 对于N根树处理器并行计算结构利用ñ<2> / X <2>三角形处理器芯片组。 使用分区的方法创建的处理器元件可扩展组织的实例。 以下合成实施例，平行于互连机构被开发的所有这些被示出为保留在构造的互连机构的尺寸X.实施例的多个三角形阵列的实现的结构的N维原始三角形阵列的功能有两个缩放神经网络仿真大规模 利用同样的大小X的处理器芯片组计算机被呈现。 最后，替代缩放机制和实施注意事项的互连机制进行了讨论。

公开(公告)号：EP0569764A3

公开(公告)日：1994-07-13

申请号：EP93106731.8

申请日：1993-04-26

申请人： International Business Machines Corporation

发明人： Pechanek, Gerald G. ,  Vassiliadis, Stamatis ,  Delgadofrias, Jose Guadelupe

IPC分类号： G06F15/80

CPC分类号： G06N3/10 ,  G06F15/8023 ,  G06N3/063

摘要： A general massively parallel computer architecture supporting neural networks is developed utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip, that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. A partitioning approach is presented first, where for a given size K and X, and K is divisible by X, it is proven that a triangular array containing K processor elements located on each edge of an equilateral triangular array can be partitioned into K/X triangular arrays of dimension X and K(K-X) / 2X ² square processor arrays of dimension X. An algorithm is presented next which partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable massively parallel computing structure for N root tree processors utilizes N ²/ X ² triangular processor group chips. Examples of using the partitioning methodology to create the scalable organization of processor elements are presented. Following these examples, an interconnection mechanism is developed which is shown to preserve the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X. Examples of the interconnection mechanism for two scaled neural network emulation massively parallel computers utilizing the same size X processor group chip are presented. Finally, an alternative scaling mechanism and implementation considerations for the interconnection mechanisms are discussed.