发明授权
- 专利标题: SUPERSCALAR RISC PROCESSOR INSTRUCTION SCHEDULING
- 专利标题(中): 命令序列顺序规划从RISC超标量
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申请号: EP93906834.2申请日: 1993-03-26
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公开(公告)号: EP0636256B1公开(公告)日: 1997-06-04
- 发明人: GARG, Sanjiv , IADONATO, Kevin, Ray
- 申请人: SEIKO EPSON CORPORATION
- 申请人地址: 4-1, Nishishinjuku 2-chome Shinjuku-ku Tokyo 163-08 JP
- 专利权人: SEIKO EPSON CORPORATION
- 当前专利权人: SEIKO EPSON CORPORATION
- 当前专利权人地址: 4-1, Nishishinjuku 2-chome Shinjuku-ku Tokyo 163-08 JP
- 代理机构: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
- 优先权: US860719 19920331
- 国际公布: WO9320505 19931014
- 主分类号: G06F9/38
- IPC分类号: G06F9/38
摘要:
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
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