发明公开
- 专利标题: Counter circuit
- 专利标题(中): 计数器电路
-
申请号: EP95109261.8申请日: 1991-05-07
-
公开(公告)号: EP0674391A3公开(公告)日: 1995-11-02
- 发明人: Hachiyama, Hiroki , Iwasawa, Takahiro , Ohmae, Masanori , Yoshida, Masakatsu , Hatano, Toshinobu , Tsuji, Masakazu
- 申请人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 申请人地址: 1006, Oaza Kadoma Kadoma-shi, Osaka-fu, 571 JP
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址: 1006, Oaza Kadoma Kadoma-shi, Osaka-fu, 571 JP
- 代理机构: Dipl.-Phys.Dr. Manitz Dipl.-Ing. Finsterwald Dipl.-Ing. Grämkow Dipl.-Chem.Dr. Heyn Dipl.-Phys. Rotermund Morgan B.Sc.(Phys.)
- 优先权: JP119431/90 19900509
- 主分类号: H03K23/00
- IPC分类号: H03K23/00 ; H03K23/50
摘要:
An image pickup apparatus includes a lens, and a solid-state image sensor for converting light which passes through the lens into an electric signal. A signal processing circuit serves to process the electric signal outputted from the solid-state image sensor. A Gray code counter serves to count pulses of a first clock signal and to generate Gray codes in response to the first clock signal. A device functions to feed a second clock signal and a synchronizing signal to the solid-state image sensor and the signal processing circuit in response to the Gray codes generated by the Gray code counter respectively. A counter circuit includes n-bit counting stages where n denotes a predetermined natural number, and a plurality of logic decoders for feeding logic outputs to input terminals of the respective counting stages, the logic outputs being equivalent to a product of a first logic output of a (k-1)-th-bit counting stage and second logic outputs of a (k-2)-th-bit counting stage and lower-bit counting stages where k denotes a natural number between 3 and n.
公开/授权文献
- EP0674391B1 Counter circuit 公开/授权日:2001-10-17
信息查询