摘要:
An image pickup apparatus includes a lens, and a solid-state image sensor for converting light which passes through the lens into an electric signal. A signal processing circuit serves to process the electric signal outputted from the solid-state image sensor. A Gray code counter serves to count pulses of a first clock signal and to generate Gray codes in response to the first clock signal. A device functions to feed a second clock signal and a synchronizing signal to the solid-state image sensor and the signal processing circuit in response to the Gray codes generated by the Gray code counter respectively. A counter circuit includes n-bit counting stages where n denotes a predetermined natural number, and a plurality of logic decoders for feeding logic outputs to input terminals of the respective counting stages, the logic outputs being equivalent to a product of a first logic output of a (k-1)-th-bit counting stage and second logic outputs of a (k-2)-th-bit counting stage and lower-bit counting stages where k denotes a natural number between 3 and n.
摘要:
An image pickup apparatus includes a lens, and a solid-state image sensor for converting light which passes through the lens into an electric signal. A signal processing circuit serves to process the electric signal outputted from the solid-state image sensor. A Gray code counter serves to count pulses of a first clock signal and to generate Gray codes in response to the first clock signal. A device functions to feed a second clock signal and a synchronizing signal to the solid-state image sensor and the signal processing circuit in response to the Gray codes generated by the Gray code counter respectively. A counter circuit includes n-bit counting stages where n denotes a predetermined natural number, and a plurality of logic decoders for feeding logic outputs to input terminals of the respective counting stages, the logic outputs being equivalent to a product of a first logic output of a (k-1)-th-bit counting stage and second logic outputs of a (k-2)-th-bit counting stage and lower-bit counting stages where k denotes a natural number between 3 and n.
摘要:
A pixel area of a megapixel solid-state color imaging device is divided into unit areas for pixel adding and all the pixels for the same color are added together in each unit area. Accordingly, the percentage of utilized pixels is raised to 100% and aliasing noise to low frequencies in a high-frequency video signal is greatly suppressed by a spatial LPF (low pass filter) effect of the pixel addition in the area units.
摘要:
An image pickup apparatus includes a lens, and a solid-state image sensor for converting light which passes through the lens into an electric signal. A signal processing circuit serves to process the electric signal outputted from the solid-state image sensor. A Gray code counter serves to count pulses of a first clock signal and to generate Gray codes in response to the first clock signal. A device functions to feed a second clock signal and a synchronizing signal to the solid-state image sensor and the signal processing circuit in response to the Gray codes generated by the Gray code counter respectively. A counter circuit includes n-bit counting stages where n denotes a predetermined natural number, and a plurality of logic decoders for feeding logic outputs to input terminals of the respective counting stages, the logic outputs being equivalent to a product of a first logic output of a (k-1)-th-bit counting stage and second logic outputs of a (k-2)-th-bit counting stage and lower-bit counting stages where k denotes a natural number between 3 and n.
摘要:
An image pickup apparatus includes a lens, and a solid-state image sensor for converting light which passes through the lens into an electric signal. A signal processing circuit serves to process the electric signal outputted from the solid-state image sensor. A Gray code counter serves to count pulses of a first clock signal and to generate Gray codes in response to the first clock signal. A device functions to feed a second clock signal and a synchronizing signal to the solid-state image sensor and the signal processing circuit in response to the Gray codes generated by the Gray code counter respectively. A counter circuit includes n-bit counting stages where n denotes a predetermined natural number, and a plurality of logic decoders for feeding logic outputs to input terminals of the respective counting stages, the logic outputs being equivalent to a product of a first logic output of a (k-1)-th-bit counting stage and second logic outputs of a (k-2)-th-bit counting stage and lower-bit counting stages where k denotes a natural number between 3 and n.