A Dynamic Random Access Memory (DRAM) includes an array of memory cells 160 arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp 166 in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs 168, 170, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs 172, 174 connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux 164 input. In this embodiment, the sense amp is connected between the mux output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied, so that cell signal margin is tested by varying cell signal, which may be selected to determine both a high and a low signal margin.