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    Dynamic random access memory
    2.
    发明公开
    Dynamic random access memory 失效
    Dynamischer Direktzugriffspeicher

    公开(公告)号：EP0766259A2

    公开(公告)日：1997-04-02

    申请号：EP96306703.8

    申请日：1996-09-16

    申请人： International Business Machines Corporation

    发明人： Debrosse, John Kenneth ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G11C29/00

    CPC分类号： G11C11/4091 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

    摘要： A Dynamic Random Access Memory (DRAM) includes an array of memory cells 160 arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp 166 in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs 168, 170, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs 172, 174 connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux 164 input. In this embodiment, the sense amp is connected between the mux output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied, so that cell signal margin is tested by varying cell signal, which may be selected to determine both a high and a low signal margin.

    摘要翻译： DRAM包括排列成行和列的存储单元的阵列，每行中的字线和每列中的一对互补位线。 字线响应行地址。 还提供了每列中提供的感测放大器，位线预充电和测试控制电路。 感测放大器，例如 一对交叉耦合的NFET连接在相应的感测使能和该对互补位线之间。 位线预充电连接到每个位线对，并连接在位线对和参考电压之间。 测试控制电路响应于测试控制信号选择性地将感测放大器禁用和位线对保持在预充电状态。 连接在感测放大器和负载使能之间的主动感测放大器负载锁定读出放大器中的数据。

    Dynamic random access memory
    4.
    发明公开
    Dynamic random access memory 失效
    动态随机存取存储器

    公开(公告)号：EP0766259A3

    公开(公告)日：1997-11-05

    申请号：EP96306703.8

    申请日：1996-09-16

    申请人： International Business Machines Corporation

    发明人： Debrosse, John Kenneth ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G11C29/00

    CPC分类号： G11C11/4091 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

    摘要： A Dynamic Random Access Memory (DRAM) includes an array of memory cells 160 arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp 166 in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs 168, 170, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs 172, 174 connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux 164 input. In this embodiment, the sense amp is connected between the mux output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied, so that cell signal margin is tested by varying cell signal, which may be selected to determine both a high and a low signal margin.

    摘要翻译： 动态随机存取存储器（DRAM）包括以行和列排列的存储器单元160的阵列，响应于行地址的每行中的字线以及每列中的一对互补位线。 该DRAM还包括连接在读出使能和该对互补位线之间的每一列中的读出放大器166。 读出放大器是一对交叉耦合的NFET168,170，NFET的源极连接到读出放大器使能。 位线预充电被连接到每对互补位线。 位线预充电连接在互补位线对和参考电压之间。 测试控制电路响应于测试控制信号选择性地将读出放大器禁用并且位线对保持在预充电状态。 在读出放大器和负载使能之间连接的有源读出放大器负载锁存读出放大器中的数据。 有源感测放大器负载是连接到感测放大器的一对交叉耦合的PFET 172,174，PFET的源极连接到负载使能。 可选地，每列可以包括多个位线对，每对都连接到多路复用器164的输入。 在这个实施例中，读出放大器连接在多路复用器输出和读出放大器使能之间。 由于控制电路使用均衡电压来禁用读出放大器，因此可以以新方式测试单元信号裕度。 不是改变读出放大器参考电压，而是改变存储在单元中的电压，以便通过改变单元信号来测试单元信号容限，可以选择单元信号来确定高信号余量和低信号余量。

    Single twist layout and method for paired line conductors of integrated circuits
    8.
    发明公开
    Single twist layout and method for paired line conductors of integrated circuits 失效
    安排具有单个Verdrillungsgebiet和用于集成电路成对线状导体的方法

    公开(公告)号：EP0697735A1

    公开(公告)日：1996-02-21

    申请号：EP95480090.0

    申请日：1995-07-13

    申请人： International Business Machines Corporation

    发明人： Debrosse, John Kenneth ,  Lary, Jenifer Edith ,  Sprogis, Edmund Juris

    IPC分类号： H01L27/108 ,  G11C7/00 ,  H01L23/522

    CPC分类号： H01L27/108 ,  G11C7/18 ,  H01L23/5225 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

    摘要： An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

    摘要翻译： 提供了用于给定的长度延伸的平行原则上的成对的线导体上的多个互连阵列布局和方法。 一个单一的交叉区域横穿所述成对的线导体中间的给定长度，worin交叉检查没有对间的电容耦合匹配每对线导体的线导体。 对内电容耦合是由两个间距分离每对线导体的线导体和一对不同的线路导体的线路导体之间设置有避免。 应用包括半导体存储器阵列，颜色：诸如DRAM的结构，和地址/数据总线worin配对真/补线导体被采用。