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    Floating bitline test mode with digitally controllable bitline equalizers
    1.
    发明公开
    Floating bitline test mode with digitally controllable bitline equalizers 有权
    Schwebende BitleitungenPrüfmodusmit Digital steuerbaren Bitleitungen-Abgleichschaltungen

    公开(公告)号：EP0907185A2

    公开(公告)日：1999-04-07

    申请号：EP98307166.3

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Kirihata, Toshiaki ,  Wong, Hing ,  Krsnki, Bozidar

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/50

    摘要： A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST ¯ signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

    摘要翻译： 该方法涉及通过提供负测试脉冲来产生用于禁止位线均衡器的虚拟定时周期。 位线均衡器禁止设置浮动位线测试模式。 行地址选通信号被使能，读操作在正常模式下启动。 在虚拟定时周期期间检测到有缺陷的位线。

    Semiconductor memory
    3.
    发明公开
    Semiconductor memory 有权
    Halbleiterspeicher

    公开(公告)号：EP0926683A2

    公开(公告)日：1999-06-30

    申请号：EP98310475.3

    申请日：1998-12-18

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Mueller, Gerhard ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C11/409 ,  G11C11/408

    CPC分类号： G11C7/18 ,  G11C8/14

    摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F 2 , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

    摘要翻译： 公开了具有分级位线和/或字线架构的半导体存储器。 在一个实施例中，具有特别适用于小于8F 2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。 第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。 每列中的多个局部位线对耦合到存储器单元，其中至少一个本地位线耦合到主位线。 在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

    Row redundancy block architecture
    4.
    发明公开
    Row redundancy block architecture 失效
    块架构行冗余

    公开(公告)号：EP0847010A2

    公开(公告)日：1998-06-10

    申请号：EP97309474.1

    申请日：1997-11-25

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： DeBrosse, John ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G06F11/20

    CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/84

    摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

    Dynamic random access memory
    5.
    发明公开
    Dynamic random access memory 失效
    Dynamischer Direktzugriffspeicher

    公开(公告)号：EP0766259A2

    公开(公告)日：1997-04-02

    申请号：EP96306703.8

    申请日：1996-09-16

    申请人： International Business Machines Corporation

    发明人： Debrosse, John Kenneth ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G11C29/00

    CPC分类号： G11C11/4091 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

    摘要： A Dynamic Random Access Memory (DRAM) includes an array of memory cells 160 arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp 166 in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs 168, 170, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs 172, 174 connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux 164 input. In this embodiment, the sense amp is connected between the mux output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied, so that cell signal margin is tested by varying cell signal, which may be selected to determine both a high and a low signal margin.

    摘要翻译： DRAM包括排列成行和列的存储单元的阵列，每行中的字线和每列中的一对互补位线。 字线响应行地址。 还提供了每列中提供的感测放大器，位线预充电和测试控制电路。 感测放大器，例如 一对交叉耦合的NFET连接在相应的感测使能和该对互补位线之间。 位线预充电连接到每个位线对，并连接在位线对和参考电压之间。 测试控制电路响应于测试控制信号选择性地将感测放大器禁用和位线对保持在预充电状态。 连接在感测放大器和负载使能之间的主动感测放大器负载锁定读出放大器中的数据。

    Semiconductor memory
    7.
    发明公开
    Semiconductor memory 有权
    半导体内存

    公开(公告)号：EP0926683A3

    公开(公告)日：2000-03-15

    申请号：EP98310475.3

    申请日：1998-12-18

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Mueller, Gerhard ,  Kirihata, Toshiaki ,  Wong, Hing

    IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C11/409 ,  G11C11/408

    CPC分类号： G11C7/18 ,  G11C8/14

    摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F 2 , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

    摘要翻译： 公开了具有分级位线和/或字线架构的半导体存储器。 在一个实施例中，具有分级位线架构的存储器，特别适用于小于8F2的单元，在每一列中包括主位线对，包括第一和第二主位线，其部分彼此垂直间隔开。 第一主位线和第二主位线在垂直方向上相对于彼此扭转，使得第一主位线交替地位于第二主位线之上和之下。 每列中的多个本地位线对耦合到存储器单元，其中至少一个本地位线耦合到主位线。 在其他实施例中，公开了分层字线配置，其包括通过开关，电触点或电路彼此电互连的主字线，次主字线和本地字线。

    Ciruit and method to externally adjust internal circuit timing
    8.
    发明公开
    Ciruit and method to externally adjust internal circuit timing 审中-公开
    Vorrichtung und Verfahren zur externen Einstellung einer internen Zeitgeberschaltung

    公开(公告)号：EP0903755A2

    公开(公告)日：1999-03-24

    申请号：EP98307137.4

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Wong, Hing ,  Kirihata, Toshiaki ,  Krsnik, Bozidar

    IPC分类号： G11C29/00 ,  G06F11/24

    CPC分类号： G11C7/22 ,  G01R31/3016

    摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

    摘要翻译： 一种使用测试模式来使用集成电路中的外部控制来控制内部信号的定时的电路和方法。 测试模式被设计为使得内部信号的定时来自外部控制，其可由测试仪任意控制。 外部信号可以应用于现有的针脚进行芯片控制，只要测试模式与集成电路的运行没有冲突。

    Method of manufacturing an integrated circuit having p-MOSFETs with different channel widths
    9.
    发明公开
    Method of manufacturing an integrated circuit having p-MOSFETs with different channel widths 失效
    制造具有不同沟道宽度的p-MOSFET的集成电路的方法

    公开(公告)号：EP0694976A3

    公开(公告)日：1996-05-22

    申请号：EP95480068.6

    申请日：1995-06-09

    申请人： International Business Machines Corporation ,  SIEMENS COMPONENTS, Inc.

    发明人： Alsmeier, Johann ,  Wong, Hing ,  Ellis, Wayne F. ,  Mandelman, Jack Allan

    IPC分类号： H01L29/36 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L29/1095 ,  H01L27/0921 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/7838

    摘要： An anomalous threshold voltage dependence on channel width measured on 0.25 µm ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. According to the invention, a set of transistors (100) having a source node (30), a drain node (40) and a common gate (20) can be constructed. Each of the N transistors in the set (10-1 to 10-N) has a channel width (Wn) chosen to provide the desired V t . The total number N is chosen to have the required current for the application in question. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V t for widths narrower than 0.4 µm. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.

    摘要翻译： 在0.25μm的接地规则生成沟槽隔离埋沟道p-MOSFET上测量的异常阈值电压与沟道宽度的关系被用于增强电路性能。 根据本发明，可以构建具有源极节点（30），漏极节点（40）和公共栅极（20）的一组晶体管（100）。 集合（10-1至10-N）中的N个晶体管中的每一个具有被选择为提供期望的Vt的沟道宽度（Wn）。总数N被选择为具有用于所述应用的所需电流。 随着沟道宽度的减小，阈值电压的幅度在宽度窄于0.4μm的Vt的预期急剧上升开始之前首先下降。 建模表明，由于在栅极氧化步骤期间的瞬态增强扩散（TED），在沟槽边界附近产生了“硼坑”，这对窄器件的截止电流造成了损失。 TED由深磷植入物产生的填隙物控制，用于闭锁抑制，扩散到装置的沟槽侧壁和顶部表面。