发明公开
- 专利标题: MICROPROCESSOR WITH PACKING OPERATION OF COMPOSITE OPERANDS
- 专利标题(中): 与PACK功能复合OPERANDS微处理器
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申请号: EP95943362申请日: 1995-12-01
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公开(公告)号: EP0795153A4公开(公告)日: 2001-11-14
- 发明人: PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
- 申请人: INTEL CORP
- 专利权人: INTEL CORP
- 当前专利权人: INTEL CORP
- 优先权: US34904794 1994-12-02
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/302 ; G06F9/315 ; G06F9/318 ; G06F7/14
摘要:
A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.
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