公开(公告)号：EP2567312B1

公开(公告)日：2017-12-27

申请号：EP11717551.3

申请日：2011-04-21

申请人： International Business Machines Corporation

发明人： BUSABA, Fadi, Yusuf ,  CURRAN, Brian, William ,  GIAMEI, Bruce, Conrad ,  JACOBI, Christian ,  ALEXANDER, Khary, Jason

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016

公开(公告)号：EP2940594A4

公开(公告)日：2016-09-21

申请号：EP13867312

申请日：2013-12-16

申请人： NEC CORP

发明人： KOBORI TOMOYOSHI

IPC分类号： G06F15/167 ,  G06F7/76 ,  G06F9/315 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F3/0647 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0689 ,  G06F7/76 ,  G06F9/30032 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F12/06 ,  G06F15/167 ,  G06F15/80

摘要： In order to provide a computation device such that declining computational efficiency, increasing circuit size, and increasing power consumption are resolved, a computation device according to the present invention comprises: first data storage means for storing data to be computed; computation processing means for executing a computation, using the data; data sort means for selecting data which is instructed from the data to be computed which is stored in the first data storage means and data which is computed with the computation processing means, appending a prescribed delay, on the basis of a parameter, to the data among the instructed data whereof a delay instruction is received, executing a sort of the instructed data on the basis of the parameter without delaying the data whereof the delay instruction is not received, and outputting the data which is computed in the computation processing means and the computation result data of the computation processing means; and second data storage means for storing the computation result data.

公开(公告)号：EP2650777A3

公开(公告)日：2014-02-05

申请号：EP13020038.9

申请日：2005-03-02

申请人： Qualcomm Incorporated

发明人： Sih, Gilbert, C. ,  Hsu, De, D. ,  Lee, Way-Shing ,  Chen, Xufeng

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3893

摘要： DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

公开(公告)号：EP1828884B1

公开(公告)日：2010-08-25

申请号：EP05824323.9

申请日：2005-12-13

申请人： Silicon Hive B.V.

发明人： GRUIJTERS, Paulus W.,F. ,  QUAX, Marcus, M.,G. ,  HELD, Ingolf

IPC分类号： G06F9/315 ,  G06F9/312 ,  G06F9/308 ,  G06F9/305 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

公开(公告)号：EP1979807A1

公开(公告)日：2008-10-15

申请号：EP07717493.6

申请日：2007-01-31

申请人： QUALCOMM Incorporated ,  Manadath, Abdulhameed A.

发明人： MANADATH, Abdulhameed A. ,  KLEIN, Anthony D. ,  MCILVAINE, Michael Scott

IPC分类号： G06F9/302 ,  G06F9/308 ,  G06F9/315

CPC分类号： G06F9/30032 ,  G06F9/3001

摘要： A processor having a unidirectional rotator configured to shift or rotate data in one direction is disclosed. The processor also includes a control unit having logic configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction, and thereby, generate the same result as if the data in the rotator had otherwise been shifted, or rotated, in the opposite direction by the shift value originally specified by the registered-based instruction. The control unit is further configured to bypass the logic and provide to the rotator a shift value specified by a register-based instruction to shift, or rotate, the data in the one direction.

公开(公告)号：EP1800211A2

公开(公告)日：2007-06-27

申请号：EP05793795.5

申请日：2005-10-05

申请人： Sony Computer Entertainment Inc.

发明人： IWATA, Eiji, SONY COMPUTER ENTERTAINMENT INC.

IPC分类号： G06F9/308 ,  G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824

摘要： A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.

摘要翻译： 提供了一种位操作处理器，系统和方法，其减少了在数据处理期间执行的操作的数量。 一个额外的寄存器被用作缓冲区。 缓冲器的位长优选大于存储器或寄存器地址中的地址边界。 比特流可以使用缓冲区本身或结合标准寄存器进行处理，具体取决于要实现的特定功能。

公开(公告)号：EP1470476A4

公开(公告)日：2007-05-30

申请号：EP03735088

申请日：2003-01-31

申请人： ARC INT

发明人： DAVIDSON SIMON ,  FERGUSON JONATHAN ,  KHAN MOHAMMED NOSHAD ,  TEMPLE ROBBIE ,  WARNES PETER ,  FUHLER RICHARD A

IPC分类号： G06F20060101 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30149 ,  G06F9/30156 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/322 ,  G06F9/3816 ,  G06F9/3867

摘要： Digital processor apparatus (1904) having an instruction set architecture (ISA) with instruction words of varying length. In the exemplary embodiment, the processor comprises an extended user-configurable RISC processor with four-stage pipeline (fetch, decode, execute, and writeback) and associated logic (1902, 1908 and 1906) that is adapted to decode and process both 32-bit and 16-bit instruction words present in a single program, thereby increasing the flexibility of the instruction set, and allowing for greater code compression and reduced memory overhead. Free-form use of the different length instructions is provided with no required mode shift. An improved instruction aligner (1908) and code compression architecture is also disclosed.

公开(公告)号：EP1431871A3

公开(公告)日：2007-01-24

申请号：EP03104930.7

申请日：2003-12-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W

IPC分类号： G06F9/315

CPC分类号： G06F9/30032

摘要： An integrated circuit device (100), comprising an input for receiving an initial data argument (D[31:0]) comprising a plurality of bits. The device also includes circuitry for providing a first shift argument (L[4:0]) indicating a number of shift positions in a first direction, the first shift argument comprising a plurality of bits, and circuitry for providing a second shift argument (R[4:0]) indicating a number of shift positions in a second direction, the second shift argument comprising a plurality of bits. The device also includes a plurality of rotate stages (ROTATE STAGE n ), each comprising an input and an output. One rotate stage (ROTATE STAGE 1), in the plurality of rotate stages, is coupled to receive the initial data argument. Each rotate stage, in the plurality of rotate stages, other than the one rotate stage, is coupled to receive a data argument from an output of another one of the rotate stages in the plurality of rotate stages. Further, each rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage in response to less than all bits of at least one of the first and second shift arguments. At least one rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage in response to a sum of respective bit positions of the first and second shift arguments.

公开(公告)号：EP1723512A2

公开(公告)日：2006-11-22

申请号：EP04743646.4

申请日：2004-08-03

申请人： ARM Limited

发明人： FORD, Simon, Andrew ,  CARPENTER, Paul, Matthew

IPC分类号： G06F9/315 ,  G06F9/308

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： A data processing system (2) is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.

摘要翻译： 提供了一种数据处理系统2，其支持移位和插入指令SLI，SRI，其用于将源数据值移位指定的移位量，然后将来自该移入位的移位值的位插入到目标值 其中该目标值内的剩余位不变。

公开(公告)号：EP1693744A1

公开(公告)日：2006-08-23

申请号：EP06110120.0

申请日：2006-02-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Singh, Rajinder P. ,  Chinnakonda, Muralidharan S. ,  Kaithamana, Bhasi

IPC分类号： G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/3816

摘要： A method comprising loading a plurality of data bytes from a data cache (304) in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus (318) using a second logic substantially coupled in parallel with the first logic, and performing a sign extension on the data bus using the second logic.

摘要翻译： 一种方法，包括响应于加载指令从数据高速缓冲存储器（304）中加载多个数据字节，使用第一逻辑确定至少一个数据字节的最高有效位，将至少一些数据字节排列到 数据总线（318），其使用基本上与第一逻辑并联的第二逻辑，以及使用第二逻辑在数据总线上执行符号扩展。