发明公开
EP0798773A3 Method of evaluating and method and apparatus for thermally processing semiconductor wafer
失效
测试，以及方法和装置，用于在半导体晶片的热处理的方法
- 专利标题： Method of evaluating and method and apparatus for thermally processing semiconductor wafer
- 专利标题（中）： 测试，以及方法和装置，用于在半导体晶片的热处理的方法
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申请号： EP97104300申请日： 1997-03-13
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公开(公告)号： EP0798773A3公开(公告)日： 1998-12-09
- 发明人: KIYAMA MAKOTO
- 申请人： SUMITOMO ELECTRIC INDUSTRIES
- 专利权人： SUMITOMO ELECTRIC INDUSTRIES
- 当前专利权人： SUMITOMO ELECTRIC INDUSTRIES
- 优先权： JP6776396 1996-03-25; JP4235197 1997-02-26
- 主分类号： G01N25/00
- IPC分类号： G01N25/00 ; C30B33/02 ; H01L21/324 ; H01L21/66
摘要：
A method of evaluating a semiconductor wafer which can provide an index as to whether slip generation is likely or not can be provided. In-plane temperature distribution of a semiconductor wafer is changed at a prescribed temperature and condition of temperature distribution generating a slip line is detected. In this manner, a range of tolerable thermal stress not generating a slip line is specified.
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