GROUP III NITRIDE SEMICONDUCTOR DEVICE AND EPITAXIAL SUBSTRATE
    5.
    发明公开
    GROUP III NITRIDE SEMICONDUCTOR DEVICE AND EPITAXIAL SUBSTRATE 审中-公开
    GRUPPE III-NITRID-HALBLEITERBAUELEMENT UND EPITAKTISCHES SUBSTRAT

    公开(公告)号:EP1876649A4

    公开(公告)日:2009-04-01

    申请号:EP06712047

    申请日:2006-01-20

    摘要: A Group III nitride semiconductor device having a structure capable of enhancing of pressure tightness. Schottky diode (11) comprises Group III nitride supporting base material (13), gallium nitride region (15) and Schottky electrode (17). The Group III nitride supporting base material (13) has conductivity. The Schottky electrode (17) forms Schottky junction in the gallium nitride region (15). The gallium nitride region (15) is superimposed on the major surface (13a) of the Group III nitride supporting base material (13). The gallium nitride region (15) has a (10-12) plane XRD full width at half maximum of = 100 sec.

    摘要翻译: 第III族氮化物半导体器件具有能够提高压力密封性的结构。 肖特基二极管(11)包括III族氮化物支撑基材(13),氮化镓区域(15)和肖特基电极(17)。 III族氮化物支撑基材(13)具有导电性。 肖特基电极(17)在氮化镓区域(15)中形成肖特基结。 氮化镓区域(15)叠置在III族氮化物支撑基材(13)的主表面(13a)上。 氮化镓区域(15)具有(10-12)平面XRD半峰全宽= 100秒。

    METHOD FOR MEASURING WITHSTAND VOLTAGE OF SEMICONDUCTOR EPITAXIAL WAFER AND SEMICONDUCTOR EPITAXIAL WAFER
    6.
    发明公开
    METHOD FOR MEASURING WITHSTAND VOLTAGE OF SEMICONDUCTOR EPITAXIAL WAFER AND SEMICONDUCTOR EPITAXIAL WAFER 审中-公开
    法测量更广泛的承受半导体晶片和外延半导体外延生长基板

    公开(公告)号:EP1503408A4

    公开(公告)日:2009-08-12

    申请号:EP03703038

    申请日:2003-01-23

    CPC分类号: H01L22/14 H01L22/34

    摘要: A method for measuring the withstand voltage of a semiconductor epitaxial wafer easily and a semiconductor epitaxial wafer exhibiting an excellent withstand voltage. In the method for measuring the withstand voltage of a semiconductor epitaxial wafer (10), withstand voltage between electrodes (12, 12) is measured using only a Schottky electrode without requiring any ohmic electrode. Since a process for forming an ohmic electrode can be eliminated, the semiconductor epitaxial wafer (10) can undergo a withstand voltage measuring test easily. Consequently, the withstand voltage of the semiconductor epitaxial wafer (10) can be measured easily. Furthermore, an unqualified wafer (10) can be removed before being delivered to an actual device fabrication process because the withstand voltage V2 between electrodes can be measured before an actual device is fabricated from the wafer (10). Consequently, loss can be reduced as compared with a conventional method where the withstand voltage V2 between electrodes is measured after an actual device is fabricated.

    GROUP III NITRIDE SEMICONDUCTOR DEVICE AND EPITAXIAL SUBSTRATE
    8.
    发明公开
    GROUP III NITRIDE SEMICONDUCTOR DEVICE AND EPITAXIAL SUBSTRATE 有权
    GRUPPE III-NITRID-HALBLEITERBAUELEMENT UND EPITAKTISCHES SUBSTRAT

    公开(公告)号:EP1746641A4

    公开(公告)日:2009-07-08

    申请号:EP06715178

    申请日:2006-03-03

    摘要: Disclosed is a group III nitride semiconductor device wherein leakage current from a Schottky electrode is reduced. In a high-electron-mobility transistor (1), a supporting substrate (3) is composed of AlN, AlGaN and GaN. An AlYGa1-YN epitaxial layer (5) has a surface roughness (Rms) of not more than 0.25 nm, and this surface roughness is defined by a 1 μm square area. A GaN epitaxial layer (7) is formed between the AlYGa1-YN supporting substrate (3) and the AlYGa1-YN epitaxial layer (5). A Schottky electrode (9) is formed on the AlYGa1-YN epitaxial layer (5). A first ohmic electrode (11) is formed on the AlYGa1-YN epitaxial layer (5), and a second ohmic electrode (13) is formed on the AlYGa1-YN epitaxial layer (5). One of the first and second ohmic electrodes (11, 13) is a source electrode, and the other is a drain electrode. The Schottky electrode (9) is a gate electrode of the high-electron-mobility transistor (1).

    摘要翻译: 公开了一种III族氮化物半导体器件,其中来自肖特基电极的泄漏电流减小。 在高电子迁移率晶体管(1)中,支撑衬底(3)由A​​lN,AlGaN和GaN组成。 AlYGa1-YN外延层(5)具有不大于0.25nm的表面粗糙度(Rms),并且该表面粗糙度由1μm的正方形面积限定。 在AlYGa1-YN支撑衬底(3)和AlYGa1-YN外延层(5)之间形成GaN外延层(7)。 肖特基电极(9)形成在AlYGa1-YN外延层(5)上。 在AlYGa1-YN外延层(5)上形成第一欧姆电极(11),在AlYGa1-YN外延层(5)上形成第二欧姆电极(13)。 第一和第二欧姆电极(11,13)之一是源电极,另一个是漏电极。 肖特基电极(9)是高电子迁移率晶体管(1)的栅电极。

    Method of evaluating and method and apparatus for thermally processing semiconductor wafer
    10.
    发明公开
    Method of evaluating and method and apparatus for thermally processing semiconductor wafer 失效
    测试,以及方法和装置,用于在半导体晶片的热处理的方法

    公开(公告)号:EP0798773A3

    公开(公告)日:1998-12-09

    申请号:EP97104300

    申请日:1997-03-13

    发明人: KIYAMA MAKOTO

    摘要: A method of evaluating a semiconductor wafer which can provide an index as to whether slip generation is likely or not can be provided. In-plane temperature distribution of a semiconductor wafer is changed at a prescribed temperature and condition of temperature distribution generating a slip line is detected. In this manner, a range of tolerable thermal stress not generating a slip line is specified.

    摘要翻译: 可以提供评价的半导体晶片,可提供索引来无论滑移产生很可能与否的方法。 面内的半导体晶片的温度分布在规定的温度被改变,并且当检测的温度分布产生的滑移线的条件。 以这种方式,指定的可容许的热应力不产生滑移线的范围内。