A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.