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公开(公告)号：EP0811921A2
公开(公告)日：1997-12-10
申请号：EP97108577.4
申请日：1997-05-28
申请人： MOTOROLA, INC.
发明人： McIntyre, Kenneth L., Jr. , Reipold, Anthony M. , Pechonis, Daniel W. , Lindquist, Steven P. , Collins, Colleen M. , Winter, Robert L.
IPC分类号： G06F12/02
CPC分类号： G06F13/4234 , G06F12/0215 , G06F12/0879 , G06F13/16 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.
摘要翻译： 数据处理系统（20）具有高性能芯片选择（HPCE）信号，其功能可编程，以基于访问占空比保持对预定数量的总线周期的有效。 选项寄存器（52）中的位允许用户在最后一个有效地址匹配之后始终执行永久，永久或持续的断言来编程HPCE，这允许用户确定高速访问和低电平之间的权衡 能量消耗。 在事务结束之前，数据处理系统（20）还提供一个总线周期的可编程芯片选择信号否定，给外部设备在下一个总线周期开始之前与当前总线周期断开连接的时间。 数据处理系统（20）还具有突发地址发生器（BAG）（55），其中可编程事务模式适用于高速缓存和预取架构类型。
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公开(公告)号：EP0811921B1
公开(公告)日：2003-02-05
申请号：EP97108577.4
申请日：1997-05-28
申请人： MOTOROLA, INC.
发明人： McIntyre, Kenneth L., Jr. , Reipold, Anthony M. , Pechonis, Daniel W. , Lindquist, Steven P. , Collins, Colleen M. , Winter, Robert L.
IPC分类号： G06F12/02
CPC分类号： G06F13/4234 , G06F12/0215 , G06F12/0879 , G06F13/16 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.
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公开(公告)号：EP1197867A2
公开(公告)日：2002-04-17
申请号：EP01129841.1
申请日：1997-05-28
申请人： MOTOROLA, INC.
发明人： McIntyre, Kenneth L. Jr. , Lindquist, Steven P. , Reipold, Anthony M. , Collins, Colleen M. , Pechonis, Daniel W. , Winter, Robert L.
IPC分类号： G06F12/02
CPC分类号： G06F13/4234 , G06F12/0215 , G06F12/0879 , G06F13/16 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.
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公开(公告)号：EP0694828A3
公开(公告)日：1996-04-03
申请号：EP95111400.8
申请日：1995-07-20
申请人： MOTOROLA, INC.
IPC分类号： G06F1/00
CPC分类号： G06F12/1466 , G11C7/24 , G11C8/20
摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.
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5.发明公开
公开(公告)号：EP0694828A2
公开(公告)日：1996-01-31
申请号：EP95111400.8
申请日：1995-07-20
申请人： MOTOROLA, INC.
IPC分类号： G06F1/00
CPC分类号： G06F12/1466 , G11C7/24 , G11C8/20
摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.
摘要翻译： 数据处理系统（10）允许授权用户通过提供存储在多个屏蔽寄存器（60,62,66）中的代码来解锁安全模式，使得系统被选择性地允许与外部设备通信。 当接收到复位信号时，选择器（48）选择第一屏蔽寄存器（60）并且从中检索第一存储的地址值和第一存储的数据值。 第一存储的地址和数据值分别通过比较器（44）与第一地址值和第一数据值进行比较。 该选择和比较的过程继续进行直到最终匹配信号被断言。 当最终匹配信号被断言时，安全信号被否定，并且系统可以与外部用户通信。
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