公开(公告)号：EP0811921A2

公开(公告)日：1997-12-10

申请号：EP97108577.4

申请日：1997-05-28

申请人： MOTOROLA, INC.

发明人： McIntyre, Kenneth L., Jr. ,  Reipold, Anthony M. ,  Pechonis, Daniel W. ,  Lindquist, Steven P. ,  Collins, Colleen M. ,  Winter, Robert L.

IPC分类号： G06F12/02

CPC分类号： G06F13/4234 ,  G06F12/0215 ,  G06F12/0879 ,  G06F13/16 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.

摘要翻译： 数据处理系统（20）具有高性能芯片选择（HPCE）信号，其功能可编程，以基于访问占空比保持对预定数量的总线周期的有效。 选项寄存器（52）中的位允许用户在最后一个有效地址匹配之后始终执行永久，永久或持续的断言来编程HPCE，这允许用户确定高速访问和低电平之间的权衡 能量消耗。 在事务结束之前，数据处理系统（20）还提供一个总线周期的可编程芯片选择信号否定，给外部设备在下一个总线周期开始之前与当前总线周期断开连接的时间。 数据处理系统（20）还具有突发地址发生器（BAG）（55），其中可编程事务模式适用于高速缓存和预取架构类型。

公开(公告)号：EP0811921B1

公开(公告)日：2003-02-05

申请号：EP97108577.4

申请日：1997-05-28

申请人： MOTOROLA, INC.

发明人： McIntyre, Kenneth L., Jr. ,  Reipold, Anthony M. ,  Pechonis, Daniel W. ,  Lindquist, Steven P. ,  Collins, Colleen M. ,  Winter, Robert L.

IPC分类号： G06F12/02

CPC分类号： G06F13/4234 ,  G06F12/0215 ,  G06F12/0879 ,  G06F13/16 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A data processing system (20) has a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match, which allows the user to determine the trade-off between high speed access and low power consumption. The data processing system (20) also provides programmable chip select signal negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. A data processing system (20) also has a burst address generator (BAG) (55), with a programmable transaction mode applicable to both cache and pre-fetch architecture types.