A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) (11) is supplied with a first eternal clock (CLK) and outputs a first internal clock (CLK1). A second clock input circuit (buffer) (12) is supplied with a second external clock (/CLK) complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit (22) generates a 1/2 phase shift signal 180° out of phase with the first internal clock (CLK). A second external clock state detection circuit judges whether the second external clock (/CLK) is input to the second clock input buffer. A switch (23) is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.