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    Control circuit arrangement for pulse-width modulated DC/DC converters and method for controlling a pulse-width modulated converter
    2.
    发明授权
    Control circuit arrangement for pulse-width modulated DC/DC converters and method for controlling a pulse-width modulated converter 有权

    公开(公告)号：EP2521263B1

    公开(公告)日：2018-09-05

    申请号：EP11164491.0

    申请日：2011-05-02

    申请人： ams AG

    发明人： Colombo, Matteo ,  Fiocchi, Carlo

    IPC分类号： H03K5/151 ,  H02M1/38

    CPC分类号： H03K5/1515 ,  H02M1/08 ,  H02M1/38 ,  H02M3/1588 ,  H03K7/08 ,  Y02B70/1466

    摘要： The present invention relates to a control circuit arrangement for pulse-width modulated DC/DC converters. The arrangement comprises a phase generator (10) for a complementary driver (20) adapted to provide respective gate signals to a first and second driver transistor in response to a control signal (p_off_pwm). A clock control circuit (30) receives a clock signal (x_clk) and a pulse-width modulated signal and provides the control signal (p_off_pwm) in response to a signal edge of the pulse-width modulated signal and the clock signal (x_clk) applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator is adapted in the first mode to provide each of the gate signals in response to the control signal and in response to the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

    DEAD TIME COMPENSATION
    3.
    发明公开
    DEAD TIME COMPENSATION 审中-公开
    死时补偿

    公开(公告)号：EP3308461A1

    公开(公告)日：2018-04-18

    申请号：EP16726318.5

    申请日：2016-06-01

    申请人： ICEPOWER A/S

    发明人： SKOV ANDERSEN, Kennet ,  JØRGENSEN, Eskil

    IPC分类号： H03F3/217 ,  H03K5/151 ,  H03K17/16

    CPC分类号： H03F3/2171 ,  H03K5/1515 ,  H03K17/162

    摘要： The invention relates to a compensator device for compensating signal dependent delay variations, including dead time and reverse recovery time, causing un-linearity in a Class-D amplifier where the compensator device comprises: a first input terminal for receiving an input pulse width modulated input PWM signal comprising pulses with falling flanks corresponding to a falling level transition and rising flanks corresponding to a rising level transition; and a second input terminal configured to receive the signal provided at an output switching node of a Class-D amplifier; an output terminal for providing a compensated output signal; and controllable delay means configured to receive and delay the pulse modulated input signal, thereby providing a delayed version of the input signal to said output terminal of the compensator device. The compensator device further comprises time measuring means configured for measuring the time between a transition of the signal provided at the output terminal of the compensator device and the corresponding transition of the signal at the output switching node of a Class-D amplifier and based on these measurements providing a control signal to the controllable delay means. An advantageous effect of the present invention is that the rising and falling level transition delays will be substantially similar thus substantially removing non-linearity and obtaining substantially correct pulse widths. The invention further relates to a corresponding method, a driver device and a Class-D amplifier.