Under one aspect of the invention, a semiconductor circuit (50) includes a first group of field effect (FET) transistors (60 and 62) of a first type (p-type) each having a body and a gate. The circuit includes a second group of field effect (FET) transistors (54 and 56) of a second type (n-type) each having a body and a gate. The circuit includes a first voltage source to selectively provide a forward bias to the bodies of the first group of FET transistors (60 and 62) during a first mode and to provide a non-forward bias to the bodies of the first group of FET transistors (60 and 62) during a second mode, and while in the first mode, the forward bias (68) is applied to the bodies of the first group of FET transistors (60 and 62) independent of voltages (A and B) applied to the gates of the first group of FET transistors (60 and 62). Under another aspect of the invention, a circuit (310) includes p-channel field effect transistors (pFET transistors) having n-type bodies electrically coupled to the ground voltage node to forward body bias the pFET transistors. A circuit includes N-channel field effect transistors (nFET transistors) having p-type bodies electrically coupled to the supply voltage node to forward body bias the nFET transistors.