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7 条记录 (耗时 0.009 秒)

    INSULATED CHANNEL FIELD EFFECT TRANSISTOR WITH AN ELECTRIC FIELD TERMINAL REGION
    1.
    发明公开
    INSULATED CHANNEL FIELD EFFECT TRANSISTOR WITH AN ELECTRIC FIELD TERMINAL REGION 审中-公开
    与电场的连接区域场效应晶体管的隔离通道

    公开(公告)号：EP1135805A4

    公开(公告)日：2003-05-21

    申请号：EP99946984

    申请日：1999-09-16

    申请人： INTEL CORP

    发明人： KESHAVARZI ALI ,  DE VIVEK K ,  NARENDRA SIVA G

    IPC分类号： H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/788 ,  H01L31/0392

    CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78645 ,  H01L29/78648

    摘要： In one embodiment, the invention includes a field effect transistor having a substrate (54), a source (S1), and a drain (D1). An electric field terminal region (52) is in the substrate. A body (64) is above the electric field terminal region between the source and drain. There is a barrier (58) between the electric field terminal region and the body. In a similar embodiment, the invention includes a field effect transistor having an insulator layer (58) and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate (G1) is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

    FORWARD BODY BIAS TRANSISTOR CIRCUITS
    4.
    发明公开
    FORWARD BODY BIAS TRANSISTOR CIRCUITS 失效
    TRANSISTOR-SCHALTUNGEN MIT SUBSTRAT-VORWÄRTSVORSPANNUNG

    公开(公告)号：EP1012971A4

    公开(公告)日：2000-09-20

    申请号：EP98930284

    申请日：1998-06-16

    申请人： INTEL CORP

    发明人： DE VIVEK K ,  KESHAVARZI ALI ,  NARENDRA SIVA G ,  BORKAR SHEKHAR Y

    IPC分类号： H01L27/092 ,  H01L29/10 ,  H03K19/0948

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948 ,  H03K2217/0018

    摘要： Under one aspect of the invention, a semiconductor circuit (50) includes a first group of field effect (FET) transistors (60 and 62) of a first type (p-type) each having a body and a gate. The circuit includes a second group of field effect (FET) transistors (54 and 56) of a second type (n-type) each having a body and a gate. The circuit includes a first voltage source to selectively provide a forward bias to the bodies of the first group of FET transistors (60 and 62) during a first mode and to provide a non-forward bias to the bodies of the first group of FET transistors (60 and 62) during a second mode, and while in the first mode, the forward bias (68) is applied to the bodies of the first group of FET transistors (60 and 62) independent of voltages (A and B) applied to the gates of the first group of FET transistors (60 and 62). Under another aspect of the invention, a circuit (310) includes p-channel field effect transistors (pFET transistors) having n-type bodies electrically coupled to the ground voltage node to forward body bias the pFET transistors. A circuit includes N-channel field effect transistors (nFET transistors) having p-type bodies electrically coupled to the supply voltage node to forward body bias the nFET transistors.

    摘要翻译： 在本发明的一个方面，一种半导体电路（50）包括具有主体和栅极的第一类型（p型）的第一组场效应晶体管（FET）晶体管（60和62）。 电路包括具有主体和门的第二类型（n型）的第二组场效应（FET）晶体管（54和56）。 电路包括第一电压源，以在第一模式期间选择性地向第一组FET晶体管（60和62）的主体提供正向偏置，并且向第一组FET晶体管的主体提供非正向偏置 （60和62），而在第一模式中，正向偏置（68）被施加到第一组FET晶体管（60和62）的主体，而不管施加到 第一组FET晶体管（60和62）的栅极。 在本发明的另一方面，电路（310）包括具有电耦合到接地电压节点的n型体的p沟道场效应晶体管（pFET晶体管），以使pFET晶体管的偏置正向。 电路包括具有电耦合到电源电压节点的p型体的N沟道场效应晶体管（nFET晶体管），以使nFET晶体管的偏置正向。

    DIGITALLY PHASE LOCKED LOW DROPOUT REGULATOR
    7.
    发明公开
    DIGITALLY PHASE LOCKED LOW DROPOUT REGULATOR 审中-公开
    低压倒灌 - 麻醉麻醉药PHASENREGELKREIS

    公开(公告)号：EP2901235A4

    公开(公告)日：2016-09-28

    申请号：EP12885472

    申请日：2012-09-25

    申请人： INTEL CORP

    发明人： RAYCHOWDHURY ARIJIT ,  SOMASEKHAR DINESH ,  TSCHANZ JAMES W ,  DE VIVEK K

    IPC分类号： G05F1/56

    CPC分类号： G05F1/577 ,  G05F1/468 ,  G05F1/56 ,  G06F1/06 ,  G06F1/26 ,  H03L7/085 ,  Y10T307/406

    摘要： Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

    摘要翻译： 描述了一种装置，包括：第一振荡器，用于产生第一时钟信号第二振荡器以产生第二时钟信号; 相位频率检测器，用于检测第一和第二时钟信号之间的相位差，并产生相位差; 以及耦合到负载的输出级，以根据相位差产生用于负载的电源。