This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.
This is achieved by providing respective adjusters (4,5) connected between a generator (7) of a program voltage (Vpp) and the cell matrix, or alternatively forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.