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    Non-volatile EEPROM type memory architecture
    2.
    发明公开
    Non-volatile EEPROM type memory architecture 审中-公开
    NichtflüchtigeEEPROM Speicherannnung

    公开(公告)号：EP1814121A1

    公开(公告)日：2007-08-01

    申请号：EP06425047.5

    申请日：2006-01-31

    申请人： STMicroelectronics S.r.l.

    发明人： Conte, Antonino ,  Annunziata, Roberto ,  Zuliani, Paola

    IPC分类号： G11C16/04 ,  G11C16/08

    CPC分类号： G11C16/0433

    摘要： A memory architecture (10) is described of the type comprising at least one matrix (2) of memory cells of the EEPROM type (3) organised in rows or word lines (WL) and columns or bit lines (BL), each memory cell (3) comprising a floating gate cell transistor (MC) and a selection transistor (TS) and being connected to a source line (SL) shared by the matrix (2). The memory cells (3) are organised in words (6), all the memory cells (3) belonging to a same word (6) being driven by a byte switch (5), in turn connected to at least one control gate line (CGT).
    Advantageously according to the invention, the memory cells (3) have accessible substrate terminals connected to a first additional line (EEW).
    Also a biasing method of a memory architecture is described.

    摘要翻译： 描述了包括以行或字线（WL）和列或位线（BL）组织的EEPROM类型（3）的存储器单元的至少一个矩阵（2）的类型的存储器架构（10），每个存储器单元 （3），包括浮置栅极单元晶体管（MC）和选择晶体管（TS），并连接到由矩阵（2）共享的源极线（SL）。 存储单元（3）以单词（6）组织，属于由字节开关（5）驱动的相同单词（6）的所有存储单元（3）依次连接到至少一个控制栅极线 CGT）。 有利地，根据本发明，存储器单元（3）具有连接到第一附加线（EEW）的可访问衬底端子。 还描述了存储器架构的偏置方法。

    Process for manufacturing a non-volatile memory device
    3.
    发明公开
    Process for manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的过程

    公开(公告)号：EP1715491A2

    公开(公告)日：2006-10-25

    申请号：EP06012616.6

    申请日：1999-04-21

    申请人： STMicroelectronics S.r.l.

    发明人： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/0433 ,  G11C16/30

    摘要： This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

    摘要翻译： 本发明涉及一种调整半导体非易失性存储器中的擦除/编程电压的方法。 存储器由具有浮动栅极，控制栅极和漏极和源极端子的存储器单元的至少一个矩阵形成，并且由行（WL）和列（BL）中的字节组织，每个字节包括一组 具有通过字节开关类型的选择元件彼此并联连接到公共控制线（CG）的各个控制栅极的单元，并且每个单元通过位开关的选择元件连接到相应的控制列（BL） 类型。 有利地，为存储单元的编程电压提供双重调整，由此擦除阶段期间的编程电压可以比写入阶段期间的编程电压更高。 这通过在阱（13）内形成位开关元件（20）并直接在衬底中形成字节开关元件（21）来实现。

    Method for differentiating the programming and erasing voltages in non volatile memory devices and corresponding memory device manufacturing process
    4.
    发明公开
    Method for differentiating the programming and erasing voltages in non volatile memory devices and corresponding memory device manufacturing process 有权
    一种用于在其非易失性存储器及其制造方法编程的分化和擦除电压的方法

    公开(公告)号：EP1047078A1

    公开(公告)日：2000-10-25

    申请号：EP99830235.0

    申请日：1999-04-21

    申请人： STMicroelectronics S.r.l.

    发明人： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

    IPC分类号： G11C16/30 ,  G11C16/12

    CPC分类号： G11C16/12 ,  G11C16/0433 ,  G11C16/30

    摘要： This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.
    This is achieved by providing respective adjusters (4,5) connected between a generator (7) of a program voltage (Vpp) and the cell matrix, or alternatively forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

    摘要翻译： 一种非易失性存储器部分（1）包括包含如行字线（WL）和列作为位线（BL）的存储单元（2）的矩阵。 控制电路（3）包括一编程​​电压产生器（7）施加到矩阵行，第一调整器（4）调整到擦除电压的（VppE）上的电压（VST）的调整器（25）和第二（5 ）的写入电压（VppW）的。 在擦除阶段的编程电压设定为比在写作阶段更高。 因此独立claimsoft包括用于制造半导体非易失性存储器，包括形成阱内的位开关元件和在所述衬底的一个字节开关直接元件的过程。

    Process for manufacturing a non-volatile memory device
    6.
    发明公开
    Process for manufacturing a non-volatile memory device 有权
    一种用于制造非易失性存储器件的方法

    公开(公告)号：EP1715491A3

    公开(公告)日：2006-11-02

    申请号：EP06012616.6

    申请日：1999-04-21

    申请人： STMicroelectronics S.r.l.

    发明人： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/0433 ,  G11C16/30

    摘要： This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

    Improved field-effect transistor and corresponding manufacturing method
    7.
    发明公开
    Improved field-effect transistor and corresponding manufacturing method 审中-公开
    Verbesserter Feldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1003222A1

    公开(公告)日：2000-05-24

    申请号：EP98830694.0

    申请日：1998-11-19

    申请人： STMicroelectronics S.r.l.

    发明人： Pio, Federico ,  Zuliani, Paola

    IPC分类号： H01L29/10 ,  H01L21/336 ,  H01L21/266

    CPC分类号： H01L29/1041 ,  H01L21/76202

    摘要： Field effect transistor (1) integrated on a semiconductor substrate (4) with a respective active area (8) comprising:

    a region of source (2) and a region of drain (3) formed in the semiconductor substrate (4),
    a channel region (5) interposed between said regions of source (2) and of drain (3) having a predefined nominal width (W N ), wherein said channel region (5) has an effective width (Weff) defined by a variable profile of doping.

    摘要翻译： 集成在具有相应有源区域（8）的半导体衬底（4）上的场效应晶体管（1）包括：源极（2）的区域和形成在半导体衬底（4）中的漏极（3）的区域，沟道 位于源极（2）的所述区域和具有预定标称宽度（WN）的漏极（3）的所述区域之间的区域（5），其中所述沟道区域（5）具有由掺杂的可变轮廓限定的有效宽度（Weff）。

    Phase-change memory device and manufacturing process thereof
    9.
    发明公开
    Phase-change memory device and manufacturing process thereof 有权
    法新社 - 佛罗伦萨

    公开(公告)号：EP1684352A1

    公开(公告)日：2006-07-26

    申请号：EP05425024.6

    申请日：2005-01-21

    申请人： STMicroelectronics S.r.l.

    发明人： Zuliani, Paola ,  Pellizzer, Fabio ,  Bez, Roberto

    IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C11/34

    CPC分类号： H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

    摘要翻译： 相变存储器件，其中存储器单元（2）以行（7）和列（6）排列并形成存储器阵列。 存储单元（2）由MOS型的选择装置（4）和连接到选择装置的相变区域（3）形成。 选择装置（4）由在半导体材料的衬底（31）中延伸并且经由沟道区（34）彼此间隔开的第一导电区域（32）和第二导电区域（33）形成， 以及连接到相应行（7）并且覆盖通道区域（34）的隔离控制区域（36）。 第一导电区域（32）连接到与行平行延伸的连接线（42），第二导电区域（33）连接到相变区域（46），相变区域连接到 相应的列（6）。 第一连接线（42）是金属互连线，并且经由源点接触区域（40）与第一导电区域（32）连接，源极接触区域（40）形成为与第一连接线（42）不同的点接触。

    A memory device with unipolar and bipolar selectors
    10.
    发明公开
    A memory device with unipolar and bipolar selectors 有权
    Speiherannnung mit unipolaren和bipolaren Auswahlschaltungen

    公开(公告)号：EP1640994A1

    公开(公告)日：2006-03-29

    申请号：EP04104595.6

    申请日：2004-09-22

    申请人： STMicroelectronics S.r.l.

    发明人： Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Benvenuti, Augusto ,  Vendrame, Loris ,  Zuliani, Paola

    IPC分类号： G11C16/02 ,  G11C11/34

    CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    摘要： A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    摘要翻译： 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。