Herein described is a successive-approximation analog-digital converter comprising a logic control circuit (1) timed by means of an external clock signal (clock). Said logic control circuit (1) comprises a register (11), which contains a first digital signal (D1) formed of N bits and obtained from a first analog-digital conversion. Said control circuit (1) is suitable for producing a second digital signal (D) formed of N bits through a second analog-digital conversion in N clock cycles. Said analog-digital converter comprises a digital-analog converter (2) which converts the second digital signal (D) sent by the logic circuit (1) to an analog signal (A), a comparator (3) which compares the analog signal (A) with an analog signal (B) which is in input to the analog-digital converter. The converter comprises a device (20, 4) which enables the increase of the analog signal (A) in output from the digital-analog converter (2) and in input to the comparator (3) of a preset value (Voffs) when the bit of the first digital signal (D1) which corresponds in position to the bit of the second digital signal (D) which must be decided in a clock cycle is zero.