利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.009 秒)

    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor
    1.
    发明公开
    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor 失效
    Schutzschaltung zur Steuerung der Gatterspannung eines Hochspannungs-LDMOS晶体管

    公开(公告)号：EP0887931A1

    公开(公告)日：1998-12-30

    申请号：EP97830296.6

    申请日：1997-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

    IPC分类号： H03K17/06

    CPC分类号： H03K17/08122 ,  H03K17/063

    摘要： A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap (Cp) capacitor charged by a diode (D1) connected to the supply node (Vs) of the circuit, by an (IO1) inverter driven by a logic control circuit in function of a first Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase where the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, comprises further a second inverter (M1, M2), functionally referred to the charging node of said bootstrap (Cp) capacitor and to the voltage of the output node (A) of said inverter (IO1) and having an input coupled to said second logic signal (UVLOb) and an output coupled to the gate node of said LDMOS transistor (LD), for preventing accidental undue switch-on of the LDMOS transistor.

    摘要翻译： 一种用于通过用作源极跟随器级的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，以通过经由自举（Cp）电容器充电的自举（Cp）电容器模拟电容的高电压充电二极管的方式被控制 和由第一低栅极驱动信号的逻辑控制电路驱动的（IO1）反相器和第二逻辑信号（UVLOb）连接的电路的供电节点（Vs）的二极管（D1） 在电源电压（Vs）低于集成电路的最小接通电压的阶段中，还包括在功能上称为所述自举（Cp）电容器的充电节点的第二反相器（M1，M2），并且 所述反相器（IO1）的输出节点（A）的电压和耦合到所述第二逻辑信号（UVLOb）的输入端和耦合到所述LDMOS晶体管（LD）的栅极节点的输出端，用于防止意外不适当的开关 - 在LDMOS晶体管上。

    Successive-approximation analog-digital converter and related operating method
    3.
    发明公开
    Successive-approximation analog-digital converter and related operating method 有权
    模拟数字万用表schrittweiserAnnäherungund entsprechendes Betriebsverfahren

    公开(公告)号：EP1150432A1

    公开(公告)日：2001-10-31

    申请号：EP00830311.7

    申请日：2000-04-27

    申请人： STMicroelectronics S.r.l.

    发明人： Bardelli, Roberto ,  Tarantola, Mario

    IPC分类号： H03M1/08

    CPC分类号： H03M1/08 ,  H03M1/462

    摘要： Herein described is a successive-approximation analog-digital converter comprising a logic control circuit (1) timed by means of an external clock signal (clock). Said logic control circuit (1) comprises a register (11), which contains a first digital signal (D1) formed of N bits and obtained from a first analog-digital conversion. Said control circuit (1) is suitable for producing a second digital signal (D) formed of N bits through a second analog-digital conversion in N clock cycles. Said analog-digital converter comprises a digital-analog converter (2) which converts the second digital signal (D) sent by the logic circuit (1) to an analog signal (A), a comparator (3) which compares the analog signal (A) with an analog signal (B) which is in input to the analog-digital converter. The converter comprises a device (20, 4) which enables the increase of the analog signal (A) in output from the digital-analog converter (2) and in input to the comparator (3) of a preset value (Voffs) when the bit of the first digital signal (D1) which corresponds in position to the bit of the second digital signal (D) which must be decided in a clock cycle is zero.

    摘要翻译： 这里描述的是包括通过外部时钟信号（时钟）定时的逻辑控制电路（1）的逐次逼近模数转换器。 所述逻辑控制电路（1）包括寄存器（11），其包含由N位形成并由第一模数转换获得的第一数字信号（D1）。 所述控制电路（1）适于通过N个时钟周期中的第二模拟数字转换产生由N位形成的第二数字信号（D）。 所述模拟数字转换器包括将由逻辑电路（1）发送的第二数字信号（D）转换为模拟信号（A）的数模转换器（2），将模拟信号 A）与模数转换器输入的模拟信号（B）。 该转换器包括一个器件（20,4），当器件（20,4）能够在数字模拟转换器（2）的输出中增加模拟信号（A），并且当输入到比较器（3）时，其输入为预设值（Voffs） 在与时钟周期中必须决定的第二数字信号（D）的位相对应的第一数字信号（D1）的位为零。

    Turn off circuit for an LDMOS in presence of a reverse current
    6.
    发明公开
    Turn off circuit for an LDMOS in presence of a reverse current 失效
    Schaltung zum Abschalten eines LDMOS晶体管在Anwesenheit von einem Gegenstrom

    公开(公告)号：EP0887933A1

    公开(公告)日：1998-12-30

    申请号：EP97830298.2

    申请日：1997-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

    IPC分类号： H03K17/06

    CPC分类号： H03K17/063 ,  H03K2217/0018

    摘要： A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance, via a bootstrap capacitor (Cp) charged by a diode at the supply voltage (Vs) of the circuit, by an inverter (IO1) driven by a logic control circuit in function of a Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase wherein the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, uses a first zener diode (Z1) to charge the bootstrap (Cp) and the source of the (LD) transistor is connected to the supply node (Vs) through a second zener diode (Z2).

    摘要翻译： 一种用于通过用作源极跟随器的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，其通过经由自举电容器（Cp）的电容器（Cp）来模拟电容器的高电压充电二极管 通过由低栅极驱动信号的功能的逻辑控制电路驱动的反相器（IO1）和在阶段期间有效的第二逻辑信号（UVLOb）的电路的电源电压（Vs）处的二极管， 电源电压（Vs）低于集成电路的最小接通电压，使用第一齐纳二极管（Z1）对自举（Cp）充电，并且（LD）晶体管的源极连接到电源节点 Vs）通过第二齐纳二极管（Z2）。

    Control of the body voltage of a high voltage LDMOS
    7.
    发明公开
    Control of the body voltage of a high voltage LDMOS 失效
    Steuerung derKörperspannungeines Hochspannungs-LDMOS晶体管

    公开(公告)号：EP0887932A1

    公开(公告)日：1998-12-30

    申请号：EP97830297.4

    申请日：1997-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Genova, Angelo ,  Tarantola, Mario ,  Cantone, Giuseppe ,  Gariboldi, Roberto

    IPC分类号： H03K17/06

    CPC分类号： H03K17/063 ,  H03K2217/0018

    摘要： A circuit for charging a capacitance (C) by mens of an LDMOS (LD) integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance and comprising a circuital device to avert the switch-on parasitic PNP transistors of the LDMOS structure during transient states, composed of a number n of junctions (d1, D2, .. , Dn) directly biased between a source node (S) and a body node (VB) of the LDMOS transistor, at least a current generator (I), referred to the potential of a ground node of the circuit, at least a switch (SW1) between said source node (S) and the first junction (D1) of said chain of directly biased junctions and a limiting resistance (R1) connected between said body node and said current generator (I) referred to ground in which the (SW1) switch is open during a charging phase of the capacitance (C) and is closed when the charging voltage of the capacitance goes over a preestablished threshold by a control signal, further comprises

    switching means (Sd1, Sd2, Sd3, Sd4) controlled by a logic signal (UVLO), active during the phase in which the supply voltage (Vs) of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging said body node (VB) with a current whose maximum value is limited to a preestablished value.

    摘要翻译： 一种用于以模拟高电压充电二极管的方式控制的LDMOS（LD）集成晶体管的电容（C）进行充电的电路，并且包括电路装置以反转LDMOS的接通的寄生PNP晶体管 由在直接偏置在LDMOS晶体管的源极节点（S）和体节点（VB）之间的n个结（d1，D2，...，Dn）组成的至少一个电流发生器（I ）指的是电路的接地节点的电位，至少在所述源极节点（S）和所述直接偏置接合链的第一结（D1）之间的开关（SW1）和连接的限制电阻（R1） 在所述体节点和所述电流发生器（I）之间称为接地，其中（SW1）开关在电容（C）的充电阶段期间断开，并且当电容的充电电压超过预先建立的阈值时闭合 控制信号还包括切换 由逻辑信号（UVLO）控制的装置（Sd1，Sd2，Sd3，Sd4）在集成电路的电源电压（Vs）低于同一集成电路的最小接通电压的相位中有效， 用于用最大值被限制为预定值的电流对所述身体节点（VB）进行充电。