A gate structure is disclosed for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer 14 on a semiconductor substrate 12, over which a polysilicon gate electrode 16 is formed. The gate structure further includes a gate conductor 18 that is electrically connected with the gate electrode through a diffusion barrier layer 20 having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.