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29 条记录 (耗时 0.016 秒)

    Low-resistance salicide fill for trench capacitors
    2.
    发明公开
    Low-resistance salicide fill for trench capacitors 有权
    Salizidfüllungmit niedrigem WiderstandfürGrabenkondensatoren

    公开(公告)号：EP0967643A3

    公开(公告)日：2003-08-20

    申请号：EP99304729.9

    申请日：1999-06-17

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Gambino, Jeffrey P. ,  Gruening, Ulrike ,  Mandelman, Jack A. ,  Radens, Carl J.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide (32) as a component of the trench electrode (26,32,34) in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

    摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。

    Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof
    8.
    发明公开
    Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof 审中-公开
    经由垂直对齐于侧壁的晶轴和方法及其制造DRAM

    公开(公告)号：EP1071129A2

    公开(公告)日：2001-01-24

    申请号：EP00306232.0

    申请日：2000-07-21

    申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

    发明人： Bronner, Gary ,  Mandelman, Jack A. ,  Gruening, Ulrike ,  Radens, Carl J.

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

    摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.

    摘要翻译： 一种动态随机存取存储器（DRAM）单元，包括具有有源晶体管器件在沟槽的侧壁上部分地设置在深沟槽存储电容器。 侧壁对准于具有沿单个晶轴的结晶取向的第一结晶学平面。 制造寻求的DRAM单元的方法，包括：（a）形成在衬底的深沟槽，（b）中沿沟槽侧壁上形成具有单一晶体取向的小平面晶体区，以及（c）形成晶体管器件部分地设置 在侧壁上的小平面晶体区。 例如通过选择以促进沿着比沿第二家庭晶轴的晶轴的第一家庭更高的氧化速率氧化条件下的局部热氧化：所述小平面晶体区可以由氧化物轴环，颜色的生长来形成。

    Providing dual work function doping
    9.
    发明公开
    Providing dual work function doping 审中-公开
    Dotierung zur Erzielung einer doppelten Austrittsarbeit

    公开(公告)号：EP0929101A1

    公开(公告)日：1999-07-14

    申请号：EP98310525.5

    申请日：1998-12-21

    申请人： International Business Machines Corporation

    发明人： Bronner, Gary Bela ,  Gambino, Jeffrey P. ,  Mandelman, Jack A. ,  Radens, Carl J. ,  Tonti, William Robert

    IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/28 ,  H01L21/225

    CPC分类号： H01L21/28035 ,  H01L21/82345

    摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

    摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选择数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些栅极结构，从而提供双功能掺杂 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，由此各个栅极结构在其顶部部分包含自对准绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。

    Method of connecting a dram trench capacitor
    10.
    发明公开
    Method of connecting a dram trench capacitor 失效
    KontaktierverfahrenfürDRAM-Grabenkondensator

    公开(公告)号：EP0791959A1

    公开(公告)日：1997-08-27

    申请号：EP97102361.9

    申请日：1997-02-13

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Stengl, Reinhard J. ,  Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Srinivasan, Radhika ,  Short, Alvin P.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

    摘要翻译： 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，电连接（90）通过有选择地控制在沟槽中存在的N型或P型掺杂剂的扩散扩散形成 通过从沟槽侧壁外延（epi）生长的单晶半导体材料（60）。 这种外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。