A DRAM memory (10) is disclosed, comprising a number of DRAM memory cells (15), which each form one, or several memory cell fields (11). Each memory cell (15) is connected to a bitline (12), or a reference bitline (13). The individual bitlines (12, 13) are connected to a read-write amplifier (30). According to the invention, in order that the read-write amplifier (30) can achieve the desired performance with high speed and reliability of performance, with the lowest possible space requirement, a space-saving read amplifier arrangement is provided, whereby the read-write amplifier (30) comprises a first read-write amplifier element (4) and a second read-write amplifier element (50), separate from the first, with the individual amplifier components (41, 42, 43, 51, 54) distributed on both read-write amplifier elements (40, 50). Several bitline pairs (16) can thus be simultaneously evaluated in a single memory cell field (11) with an individual read-write amplifier.