公开(公告)号：EP4020477B1

公开(公告)日：2024-10-23

申请号：EP21818325.9

申请日：2021-03-01

发明人： SHANG, Weibing

IPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G11C11/409 ,  G11C11/419 ,  G11C13/00

公开(公告)号：EP4042422B1

公开(公告)日：2024-07-10

申请号：EP20917463.0

申请日：2020-02-06

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  H03F3/45

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2203/4561420130101 ,  H03F2203/4556220130101 ,  H03F2203/4558820130101

公开(公告)号：EP4092673B1

公开(公告)日：2024-01-31

申请号：EP21859351.5

申请日：2021-07-21

发明人： SU, Hsin-cheng

IPC分类号： G11C29/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C5/14 ,  G11C11/4074

公开(公告)号：EP3933839B1

公开(公告)日：2024-01-10

申请号：EP21773437.5

申请日：2021-01-27

发明人： SHANG, Weibing ,  LI, Hongwen

IPC分类号： G11C11/408 ,  G11C11/4097 ,  G11C11/4091

公开(公告)号：EP3953934A1

公开(公告)日：2022-02-16

申请号：EP20787018.9

申请日：2020-03-11

申请人： MICRON TECHNOLOGY, INC.

发明人： BEDESCHI, Ferdinando ,  SCHIPPERS, Stefan, Frederik

IPC分类号： G11C8/14 ,  G11C11/4091 ,  G11C5/06 ,  H01L27/108

公开(公告)号：EP2622603B1

公开(公告)日：2020-09-09

申请号：EP11784532.1

申请日：2011-10-03

申请人： Qualcomm Incorporated

发明人： CHEN, Nan ,  CHEN, Zhiqin ,  CHABA, Ritu

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/08

公开(公告)号：EP3025346B1

公开(公告)日：2019-01-02

申请号：EP14829677.5

申请日：2014-07-10

申请人： Micron Technology, Inc.

发明人： MANNING, Troy A.

IPC分类号： G11C15/04 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096

公开(公告)号：EP3151244A1

公开(公告)日：2017-04-05

申请号：EP16191130.0

申请日：2011-08-03

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Inoue, Hiroki ,  Kato, Kiyoshi ,  Matsuzaki, Takanori ,  Nagatsuka, Shuhei

IPC分类号： G11C16/04 ,  G11C11/405 ,  H01L29/66 ,  H01L29/786 ,  G11C11/404 ,  G11C16/24 ,  H01L21/02 ,  H01L21/441 ,  H01L21/425 ,  H01L21/477 ,  H01L27/108 ,  H01L27/12 ,  G11C16/08 ,  G11C11/4091 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/11526

CPC分类号： H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

摘要： A method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc; implanting oxygen ions into the oxide semiconductor layer; performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen; performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer; wherein the second heat treatment is performed after the first heat treatment.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘表面上形成氧化物半导体层，所述氧化物半导体层包括沟道形成区，所述氧化物半导体层含有铟，锡和锌; 将氧离子注入到氧化物半导体层中; 在含氮的气氛中对氧化物半导体层进行第一次热处理; 在氧气的气氛中对氧化物半导体层进行第二次热处理，使得氧化物半导体层包含过量的氧，氧化物半导体层能够补偿氧化物半导体层中的氧缺乏; 其中所述第二热处理在所述第一热处理之后进行。

公开(公告)号：EP2764515A1

公开(公告)日：2014-08-13

申请号：EP12838980.6

申请日：2012-10-03

申请人： Conversant Intellectual Property Management Inc.

发明人： CHOI, Byoung Jin

IPC分类号： G11C11/4094 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.

公开(公告)号：EP2751808A1

公开(公告)日：2014-07-09

申请号：EP12827743.1

申请日：2012-08-27

申请人： Rambus Inc.

发明人： VOGELSANG, Thomas

IPC分类号： G11C11/4063 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097

摘要： Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.