发明公开
EP1269323A2 MULTI-TIERED MEMORY BANK HAVING DIFFERENT DATA BUFFER SIZES WITH A PROGRAMMABLE BANK SELECT
审中-公开
不同的数据缓冲区的大小和一个可编程的银行选择多级内存BANK
- 专利标题： MULTI-TIERED MEMORY BANK HAVING DIFFERENT DATA BUFFER SIZES WITH A PROGRAMMABLE BANK SELECT
- 专利标题（中）： 不同的数据缓冲区的大小和一个可编程的银行选择多级内存BANK
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申请号： EP01926544.6申请日： 2001-03-30
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公开(公告)号： EP1269323A2公开(公告)日： 2003-01-02
- 发明人: RAMAGOPAL, Hebbalalu, S. , ALLEN, Michael , FRIDMAN, Jose , HOFFMAN, Marc
- 申请人： INTEL CORPORATION , ANALOG DEVICES, INCORPORATED
- 申请人地址： 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 专利权人： INTEL CORPORATION,ANALOG DEVICES, INCORPORATED
- 当前专利权人： INTEL CORPORATION,ANALOG DEVICES, INCORPORATED
- 当前专利权人地址： 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 代理机构： Loveless, Ian Mark
- 优先权： US541114 20000331
- 国际公布： WO01075607 20011011
- 主分类号： G06F12/08
- IPC分类号： G06F12/08
摘要：
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor
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