公开(公告)号：EP1402394A2

公开(公告)日：2004-03-31

申请号：EP01924581.0

申请日：2001-04-02

申请人： INTEL CORPORATION ,  ANALOG DEVICES, INCORPORATED

发明人： ALDRICH, Bradley, C. ,  FRIDMAN, Jose ,  MEYER, Paul

IPC分类号： G06F15/78 ,  G06F9/302 ,  G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/509 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/7857 ,  G06F2207/382 ,  G06F2207/3828

摘要： A system comprising: a bus; and a digital signal processor comprising: a multiplier having a first structure and a second structure, the first structure processing data up to n-bits and the second structure processing data up to (n/2)-bits; and a data size selector which configures the multiplier into the first structure of a single n-bit multiplier when the data is greater than (n/2)-bits and configures the multiplier into the second structure of two (n/2)-bit multipliers when the data is (n/2)-bits or less.

公开(公告)号：EP1269323A2

公开(公告)日：2003-01-02

申请号：EP01926544.6

申请日：2001-03-30

申请人： INTEL CORPORATION ,  ANALOG DEVICES, INCORPORATED

发明人： RAMAGOPAL, Hebbalalu, S. ,  ALLEN, Michael ,  FRIDMAN, Jose ,  HOFFMAN, Marc

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/0846 ,  G06F2212/2515

摘要： An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor

公开(公告)号：EP1137983B1

公开(公告)日：2003-06-04

申请号：EP99964951.0

申请日：1999-10-29

申请人： ANALOG DEVICES, INCORPORATED

发明人： GARDE, Douglas ,  ZATSMAN, Alexei ,  LEZEROVITZ, Aryeh ,  GREENFIELD, Zvi ,  LEVINE, David, R. ,  FRIDMAN, Jose

IPC分类号： G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

公开(公告)号：EP1188112A2

公开(公告)日：2002-03-20

申请号：EP00930720.8

申请日：2000-05-12

申请人： ANALOG DEVICES, INCORPORATED

发明人： ANDERSON, William, Caroll ,  EDMONDSON, John ,  FRIDMAN, Jose ,  HOFFMAN, Marc ,  RIVIN, Russel, L.

IPC分类号： G06F9/302

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30149 ,  G06F9/3873 ,  G06F9/3875 ,  G06F9/3887 ,  G06F9/3893

摘要： A method for determining an output of a finite impulse response digital filter having L filter coefficients in response to a set of M input samples, comprising the steps of: (a) loading a first input sample into a first location in a first register; (b) loading a second input sample into a second location in said first register; (c) loading two coefficients into a second register; (d) computing intermediate results using the contents of the first and second registers; (e) loading a new input sample into the first location in said first register; (f) computing intermediate results using the contents of the first and second registers; (g) repeating steps (b) - (f) for L iterations to provide two output samples; and (h) repeating steps (a) - (g) for M/2 iterations to provide M output samples.

公开(公告)号：EP1137983A2

公开(公告)日：2001-10-04

申请号：EP99964951.0

申请日：1999-10-29

申请人： ANALOG DEVICES, INCORPORATED

发明人： GARDE, Douglas ,  ZATSMAN, Alexei ,  LEZEROVITZ, Aryeh ,  GREENFIELD, Zvi ,  LEVINE, David, R. ,  FRIDMAN, Jose

IPC分类号： G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

摘要： A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at laest one control information register for storing control information used by the bit transfer mechanism.