The circuit comprises a first ring oscillator (OSC1) comprising an odd number of inverting elements, a delay element (DA) and an output terminal (N); the delay element (DA) responds to a pulse at its input (IN-DA) with a predetermined time delay (d(DA)) with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator (OSC2) equal to the first, having an output terminal connected to the output terminal (N) of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output (N) of the first and the second oscillator. At least one of the inverting elements of the first oscillator (OSC1) and at least one of the inverting elements of the second oscillator (OSC2) form part of the bistable logic circuit.