利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.016 秒)

    Switched capacitance circuit
    2.
    发明公开
    Switched capacitance circuit 有权
    开关电容电路和模拟/数字转换器，包括该电路

    公开(公告)号：EP2061152A1

    公开(公告)日：2009-05-20

    申请号：EP08105569.1

    申请日：2004-05-05

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Zamprogno, Marco

    IPC分类号： H03M1/00

    CPC分类号： G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

    摘要： A switched capacitance circuit including:
    - a switched capacitance section (SC), capable of receiving as input a signal (V IMP , V IMM ) and carrying out a sampling of said signal, the section comprising at least one group (AR, AR') of capacitors (Ca, Cb, Cc, Ca', Cb', Cc') each of which has a terminal connected to a common node (NS, NS');
    - at least an operational stage (CMP) including at least an input terminal (IN, IN') connected to said common node (NS, NS'), the operational stage (CMP) providing a current to said common node (NS, NS') for charging said group (AR, AR') of capacitors during a sampling time interval of said signal (V INP , V INM ).
    The circuit further includes an auxiliary circuit (ANC) connected to said common node (NS, NS') and capable of being activated/deactivated by an enabling signal (PRECH) for injecting a further current into said common node (NS, NS') and increasing the current provided to said common node (NS, NS') during at least one time interval equal to a fraction of said sampling interval.

    摘要翻译： 一种开关电容电路，包括： - 一个开关电容部分（SC），能够接收作为输入的信号（V IMP，V IMM）和进行所述信号的一个取样的，所述部分包括至少一组（AR，AR' ）电容器（CA，CB，抄送钙 'CB'，Cc的 '（），其中每个具有连接到公共节点NS，NS终端'）; - 至少在包括操作阶段（CMP）至少到输入端子“连接到所述公共节点（NS，NS），运算步骤（CMP）提供电流到所述公共节点（NS，NS（IN，IN）” “），用于充电所述组（AR，AR”，所述信号（V INP，V INM）的采样时间间隔期间电容）。 该电路还包括连接到所述公共节点（NS，NS“）辅助电路（ANC）上（并能够被激活/通过在使能信号（PRECH）用于注入另一电流到所述公共节点NS，NS）去激活” 并且在至少一个时间间隔等于所述取样间隔的分数增加提供给所述公共节点（NS，NS“）的电流。

    Low consumption and low noise analog-digital converter of the SAR type and method of employing it
    5.
    发明公开
    Low consumption and low noise analog-digital converter of the SAR type and method of employing it 有权
    对于SAR类型的具有低消耗量和噪声的模拟/数字转换的方法和装置

    公开(公告)号：EP1583244A1

    公开(公告)日：2005-10-05

    申请号：EP04425241.9

    申请日：2004-04-01

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

    IPC分类号： H03M1/46

    CPC分类号： H03M1/002 ,  H03M1/462

    摘要： The described converter comprises switched-capacitor quantization means (DAC, COMP) for receiving an analog quantity to be converted (VIN), a register (REG) for a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register (REG) the digital quantity to be furnished as output (OUTBUS). With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator (CLK-GEN) comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals (REGBUS0, REGBUS1) emitted by the logic means.
    Also described is a method of using the converter that comprises the following phases: loading of the analog quantity (VIN) in the quantization means (DAC, COMP), memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means (LOG).

    Clock-pulse generator circuit
    6.
    发明公开
    Clock-pulse generator circuit 有权
    Taktimpulsgenerator

    公开(公告)号：EP1566888A1

    公开(公告)日：2005-08-24

    申请号：EP04425100.7

    申请日：2004-02-18

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Nagari, Angelo

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00071

    摘要： The circuit comprises a first ring oscillator (OSC1) comprising an odd number of inverting elements, a delay element (DA) and an output terminal (N); the delay element (DA) responds to a pulse at its input (IN-DA) with a predetermined time delay (d(DA)) with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator (OSC2) equal to the first, having an output terminal connected to the output terminal (N) of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output (N) of the first and the second oscillator. At least one of the inverting elements of the first oscillator (OSC1) and at least one of the inverting elements of the second oscillator (OSC2) form part of the bistable logic circuit.

    摘要翻译： 该电路包括包括奇数个反相元件的第一环形振荡器（OSC1），延迟元件（DA）和输出端子（N）; 延迟元件（DA）相对于输入脉冲的预定边缘以预定的时间延迟（d（DA））在其输入端（IN-DA）处响应脉冲，并且相对于另一边缘基本上没有时间延迟 的输入脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括等于第一环路振荡器（OSC2）的第二环形振荡器（OSC2），其具有连接到输出端子（N）的输出端子 第一振荡器和双稳态逻辑电路，其输出端连接到第一和第二振荡器的公共输出端（N）。 第一振荡器（OSC1）的反相元件和第二振荡器（OSC2）的反相元件中的至少一个的至少一个形成双稳态逻辑电路的一部分。

    Digital system with an output buffer with a switching current settable to load-independent constant values
    8.
    发明公开
    Digital system with an output buffer with a switching current settable to load-independent constant values 审中-公开
    一种数字系统具有输出缓冲器电路具有可调节的常数和负载无关的输出电流

    公开(公告)号：EP1372265A1

    公开(公告)日：2003-12-17

    申请号：EP02425378.3

    申请日：2002-06-10

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K17/166 ,  H03K17/164

    摘要： A digital system comprises a digital data processing unit (PROC), at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit (13) connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means (14, 15, IGEN1, IGEN2) for fixing the switching current to a value that is substantially constant and independent of the load and means (SN2-4, SP2-4) for selectively setting the value of the switching current and the processing unit (PROC) comprises means (REG) for storing a predetermined parameter; said means (REG) are connected to the selective setting means (SN2-4, SP2-4) for setting the values of the switching current as functions of the predetermined parameter.

    摘要翻译： 一种数字系统，包括一个数字数据处理单元（PROC），连接到所述处理单元响应于来自所述处理单元和至少一个用户单元（13）到达的数字信号，以产生输出信号的至少一个输出缓冲器连接作为输出缓冲 负载。 与以确保没有输出缓冲区的切换电流的图可以被设置为不同的值，输出缓冲器包括装置（14，15，IGEN1，IGEN2），用于切换电流固定为一个值那样基本上是恒定的和独立的 负载和用于有选择地设定切换电流和所述处理单元（PROC）的值的装置（SN2-4，SP2-4）包括用于存储预定参数的装置（REG）; 所述装置（REG）被连接到所述选择性设定装置（SN2-4，SP2-4）用于设定切换电流的值作为预定参数的功能。

    High resolution and low power consumption digital-analog converter
    10.
    发明公开
    High resolution and low power consumption digital-analog converter 审中-公开
    Hochauflösender数字模拟Wandler mit geringem Leistungsverbrauch

    公开(公告)号：EP1710917A1

    公开(公告)日：2006-10-11

    申请号：EP06116241.8

    申请日：2003-03-14

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Nicollini, Germano ,  Martignone, Riccardo

    IPC分类号： H03M1/68

    CPC分类号： H03M1/687 ,  H03M1/68 ,  H03M1/745 ,  H03M1/765

    摘要： A digital to analog converter to convert into an analog quantity a digital code of L bits, comprising
    - a first group of L current generators codified in binary form (MDON-MD2N),
    - first selection means (SDON-SD2N) of the L current generators,
    - means for conveying onto a common output node (N3) the current (IL) of the selected generators,
    - control means (TRANSCOD-3BIT') to selectively operate the selection means (SD0N-SD2N) according to the digital code of L bits.
    The converter further comprises a second group of L current generators (MD0P-MD2P) codified in binary form and second selection means (SD0P-SD2P) of the second group of L current generators.
    The control means comprise a selection logic that alternatively habilitates the use of the first or the second group of generators according to whether the digital code to be converted does (D11=1) or does not (D11=0) exceed, respectively, a predetermined value.

    摘要翻译： 一种数模转换器，用于将L位的数字码转换为模拟量，包括：以二进制形式编码的第一组L电流发生器（MDON-MD2N），L电流的第一选择装置（SDON-SD2N） 发电机， - 用于将所选发电机的电流（IL）传送到公共输出节点（N3）的装置， - 控制装置（TRANSCOD-3BIT'），以根据数字代码选择性地操作选择装置（SD0N-SD2N） L位。 转换器还包括以二进制形式编码的第二组L电流发生器（MD0P-MD2P）和第二组L电流发生器的第二选择装置（SD0P-SD2P）。 所述控制装置包括选择逻辑，所述选择逻辑根据所述要转换的数字码是否（D11 = 1）或不（D11 = 0）分别超过预定的 值。