- 专利标题: Semiconductor integrated circuit and fabrication process thereof
-
申请号: EP05011032.9申请日: 2005-05-20
-
公开(公告)号: EP1679743B1公开(公告)日: 2018-10-10
- 发明人: Hatada, Akiyoshi , Katakami, Akira , Tamura, Naoyoshi , Shimamune, Yosuke , Shima, Masashi , Ohta, Hiroyuki
- 申请人: Fujitsu Semiconductor Limited
- 申请人地址: 2-100-45 Shin-Yokohama Kohoku-ku Yokohama-shi Kanagawa 222-0033 JP
- 专利权人: Fujitsu Semiconductor Limited
- 当前专利权人: Fujitsu Semiconductor Limited
- 当前专利权人地址: 2-100-45 Shin-Yokohama Kohoku-ku Yokohama-shi Kanagawa 222-0033 JP
- 代理机构: Hoffmann Eitle
- 优先权: JP2005004405 20050111
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/8238 ; H01L29/78
摘要:
A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in the second device region.
公开/授权文献
信息查询
IPC分类: