公开(公告)号：EP1679743B1

公开(公告)日：2018-10-10

申请号：EP05011032.9

申请日：2005-05-20

申请人： Fujitsu Semiconductor Limited

发明人： Hatada, Akiyoshi ,  Katakami, Akira ,  Tamura, Naoyoshi ,  Shimamune, Yosuke ,  Shima, Masashi ,  Ohta, Hiroyuki

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/933

摘要： A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in the second device region.

公开(公告)号：EP1693897B1

公开(公告)日：2018-03-07

申请号：EP05010736.6

申请日：2005-05-18

申请人： Fujitsu Semiconductor Limited

发明人： Tamura, Naoyoshi ,  Shimamune, Yosuke ,  Hatada, Akiyoshi ,  Katakami, Akira ,  Shima, Masashi

IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L29/165 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.