发明公开
EP1733425A1 METHOD FOR INTEGRATING SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE AND RELATED STRUCTURE
审中-公开
方法SIGE NPN和垂直PNP组分对基材和相关结构整合
- 专利标题: METHOD FOR INTEGRATING SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE AND RELATED STRUCTURE
- 专利标题(中): 方法SIGE NPN和垂直PNP组分对基材和相关结构整合
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申请号: EP05725796.6申请日: 2005-03-17
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公开(公告)号: EP1733425A1公开(公告)日: 2006-12-20
- 发明人: HURWITZ, Paul, D. , RING, Kenneth, M. , HU, Chun , KALBURGE, Amol
- 申请人: Newport Fab, LLC DBA Jazz Semiconductor
- 申请人地址: 4321 Jamboree Road Newport Beach, CA 92660 US
- 专利权人: Newport Fab, LLC DBA Jazz Semiconductor
- 当前专利权人: Newport Fab, LLC DBA Jazz Semiconductor
- 当前专利权人地址: 4321 Jamboree Road Newport Beach, CA 92660 US
- 代理机构: Kindermann, Peter
- 优先权: US821425 20040409
- 国际公布: WO2005104224 20051103
- 主分类号: H01L21/8228
- IPC分类号: H01L21/8228
摘要:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
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