公开(公告)号：EP3800669A1

公开(公告)日：2021-04-07

申请号：EP20198015.8

申请日：2020-09-24

申请人： Analog Devices International Unlimited Company

发明人： COYNE, Edward ,  BRANNICK, Alan ,  TOOHER, Shane ,  O HANNAIDH, Breandan Pol Og ,  O'SULLIVAN, Catriona Marie ,  GEARY, Shane

IPC分类号： H01L29/737 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L21/331 ,  H01L27/082 ,  H01L21/8228

摘要： A charge control structure (1001, 1002) is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate (1002) above the upper surface of the collector (1008) and dielectrically isolated from the upper surface of the collector and a vertical field plate (1001) which is at a side of the collector (1008) and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base (1003) as well as the field-plates (1001, 1002) in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

公开(公告)号：EP2100330B1

公开(公告)日：2012-03-07

申请号：EP07847998.7

申请日：2007-12-07

申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik

发明人： KNOLL, Dieter ,  HEINEMANN, Bernd ,  EHWALD, Karl-Ernst

IPC分类号： H01L21/8228 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

摘要： Complementary bipolar semiconductor device (Cbi semiconductor device) with a substrate of a first conductivity type, active bipolar transistor regions in the substrate in which the base, emitter, and collector of vertical bipolar transistors are arranged; vertical epitaxial base npn bipolar transistors in a first subset of the active bipolar transistor regions; vertical epitaxial base pnp bipolar transistors in a second subset of the active bipolar transistor regions; collector contact regions which are each arranged bordering on an active bipolar transistor region; and flat field isolation regions which each laterally bound the active bipolar transistor regions and the collector contact regions. A flat field isolation region of a first type with a first extended depth in the direction of the substrate interior is arranged between the first or the second or both the first and the second subset of active bipolar transistor regions on one side and the adjacent collector contact regions on the other, and flat field isolation areas of a second type, with a second extended depth larger than the first, bound the active bipolar transistor regions and the collector contact regions, viewed in cross section, on the sides thereof facing away from each other.

公开(公告)号：EP1576651A4

公开(公告)日：2009-09-16

申请号：EP03759404

申请日：2003-09-19

申请人： ADVANCED ANALOGIC TECH INC

发明人： WILLIAMS RICHARD K ,  CORNELL MICHAEL E ,  CHAN WAI TIEN

IPC分类号： H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L27/082 ,  H01L21/76 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L27/102 ,  H01L27/105

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

公开(公告)号：EP1733425A1

公开(公告)日：2006-12-20

申请号：EP05725796.6

申请日：2005-03-17

申请人： Newport Fab, LLC DBA Jazz Semiconductor

发明人： HURWITZ, Paul, D. ,  RING, Kenneth, M. ,  HU, Chun ,  KALBURGE, Amol

IPC分类号： H01L21/8228

CPC分类号： H01L21/82285 ,  H01L21/8228 ,  H01L27/0826

摘要： According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

公开(公告)号：EP1116269A4

公开(公告)日：2005-06-22

申请号：EP99945182

申请日：1999-08-23

申请人： BURR BROWN CORP

发明人： DROBNY VLADIMIR F ,  BAO KEVIN X

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/331 ,  H01L21/8228 ,  H01L21/8249 ,  H01L21/8238

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02661 ,  H01L21/8249

摘要： An epitaxial layer is formed on a p type silicon substrate (30) in which a plurality of P+ buried layer regions (31, 33), a plurality of N+ buried layer regions (32), and a P+ field layer region (33) occupying most of the substrate (30) surface are diffused. Following a plurality of heating steps, a first thin intrinsic epitaxial cap layer (36) is formed, a first gas purge cycle is performed, a second thin epitaxial layer cap layer (37) is formed, a second gas purge cycle is performed, and an N- epitaxial layer (38) is deposited.

公开(公告)号：EP1187194B1

公开(公告)日：2007-03-07

申请号：EP01307575.9

申请日：2001-09-06

申请人： SANYO ELECTRIC CO. LTD

发明人： Takada, Tadayoshi ,  Kitamura, Osamu ,  Okawa, Shigeaki ,  Hata, Hirotsugu ,  Fujinuma, Chikao

IPC分类号： H01L21/8228 ,  H01L21/86 ,  H01L21/762

CPC分类号： H01L21/76297 ,  H01L21/76264 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：EP1747582A2

公开(公告)日：2007-01-31

申请号：EP05749795.0

申请日：2005-05-10

申请人： Amtel Corporation

发明人： CHAUDHRY, Muhammad, I. ,  CARVER, Damian, A.

IPC分类号： H01L21/8238 ,  H01L29/788 ,  H01L21/00 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/8228 ,  H01L21/28 ,  H01L29/76

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

摘要： The present invention is an electronic memory cell (200) and a method for the cell’s fabrication comprising a first transistor (201) configured to be coupled to a bit line. The first transistor (201) has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell (200). A second transistor (203) is configured to operate as a memory transistor and is coupled to the first transistor (201). The second transistor (203) is further configured to be programmable with a voltage about equal to a voltage on the bit line.

公开(公告)号：EP0881689B1

公开(公告)日：2002-08-07

申请号：EP97830260.2

申请日：1997-05-30

申请人： STMicroelectronics S.r.l.

发明人： Pinto, Angelo ,  Alemanni, Carlo

IPC分类号： H01L29/735 ,  H01L21/331 ,  H01L27/082 ,  H01L21/8228

CPC分类号： H01L29/6625 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/735

公开(公告)号：EP0740335A3

公开(公告)日：1998-07-08

申请号：EP96106260

申请日：1996-04-19

申请人： SIEMENS AG

发明人： KERBER MARTIN DR

IPC分类号： H01L21/02 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/082 ,  H01L27/092 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L29/7317

摘要： Herstellungsverfahren für laterale Bipolartransistoren auf SOI-Substrat, bei dem auf eine mit einer Grunddotierung versehene Mesa (3) eine stegförmige Gate-Elektrode (8/9) aufgebracht und ganzflächig mit einer TEOS-Schicht (10) mit als Spacer (11, 12) fungierenden vertikalen Anteilen an den Flanken dieser Gate-Elektrode bedeckt wird. Unter Verwendung von Lackmasken (13, 14) werden Dotierstoffe für einen Kollektor-Bereich (4) und einen Emitter-Bereich (6) eingebracht. Die Basisimplantierung erfolgt nach dem Entfernen der TEOS-Schicht (10) im Bereich des Spacers (11) längs eines Randes der Gate-Elektrode.

公开(公告)号：EP0792514A4

公开(公告)日：1998-06-17

申请号：EP95940602

申请日：1995-11-02

申请人： ANALOG DEVICES INC

发明人： LAPHAM JEROME F ,  SCHARF BRAD W

IPC分类号： H01L21/761 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L21/265 ,  H01L29/00

CPC分类号： H01L21/761 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/7322

摘要： Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well (11) is formed in a P-type substrate (10). P-type dopant is implanted in the N-well (11) to become a sub-collector (12) for a pnp transistor. N-type dopant is implanted in the substrate (10) in a location laterally displaced from the N-well (11) to become a sub-collector (18) for an npn transistor. N-type material is implanted in the N-well (11) to begin the formation of an isolation wall (16) for the pnp transistor. A P-type epitaxial (epi) layer (20) then is grown over the P-type substrate (10). N-type material is implanted in the epi layer (20) to complete the isolation wall (22) for the pnp transistor, and to complete the collector (24) for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer (20) to form the bases (30, 34) and emitters (32, 40) for the npn and pnp transistors.

摘要翻译： 过程用于与结隔离互补双极晶体管制造的集成电路（IC）芯片。 在N阱的过程中的基板P型形成。 P型掺杂物在N阱植入以成为一个子集电极为PNP晶体管。 N型掺杂剂在从N阱移位的位置处尾盘反弹基板植入成为在子集电极NPN晶体管。 N型材料在N阱注入开始的隔离壁的供PNP晶体管的形成。 P型外延（外延）层，然后在P型衬底上生长。 N型材料注入到外延层，以完成所述PNP晶体管的隔离壁，并完成为NPN晶体管的集电极。 P型和N型材料，从而在P型外延层，以形成用于NPN和PNP晶体管的基极和发射极植入。