A delay-locked loop 300 that includes: an adjustable frequency source ( 320 ) for generating a clock signal ( 322 ) having an adjustable frequency; an adjustment and tap selection controller ( 310 ) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line ( 330 ) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit ( 370 ) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.