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31 条记录 (耗时 0.014 秒)

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND CONTROL METHOD OF SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND CONTROL METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件，半导体系统和半导体器件的控制方法

    公开(公告)号：EP3301541A1

    公开(公告)日：2018-04-04

    申请号：EP17185297.3

    申请日：2017-08-08

    申请人： Renesas Electronics Corporation

    发明人： Fukuoka, Kazuki ,  Uemura, Toshifumi ,  Kitaji, Yuko ,  Okazaki, Yosuke ,  Murayama, Akira

    IPC分类号： G06F1/26 ,  G06F1/28 ,  G01R31/28 ,  H03K5/133

    摘要： An object of the present invention is to provide a semiconductor device, a semiconductor system, and a control method of a semiconductor device capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

    摘要翻译： 本发明的目的是提供一种能够准确地监视要监视的电路的最低工作电压的半导体器件，半导体系统和半导体器件的控制方法。 根据一个实施例，半导体系统的监视器单元包括电压监视器，该电压监视器由与供给到作为待监视电路的内部电路的第一电源电压不同的第二电源电压驱动，并且监视第一电源 电压以及由第一电源电压驱动并且监视内部电路中的关键路径的信号传播时间段的延迟监视器。

    CUSTOMIZABLE LOGIC CELL WITH METHODS TO FORM SAME
    6.
    发明公开
    CUSTOMIZABLE LOGIC CELL WITH METHODS TO FORM SAME 审中-公开

    公开(公告)号：EP4462679A1

    公开(公告)日：2024-11-13

    申请号：EP23208142.2

    申请日：2023-11-07

    申请人： GlobalFoundries U.S. Inc.

    发明人： Chinthu, Siva Kumar ,  Ara, Venu Gopal Reddy ,  Dwivedi, Devesh

    IPC分类号： H03K5/133 ,  H03K19/0185 ,  H03K19/20

    摘要： Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure (100) of the disclosure includes a first pair of complementary transistors (112) connected in series between a first voltage node (V1) and a second voltage node (V2). Each transistor of the first pair includes a gate coupled to a first input node (N1). A second pair of complementary transistors (114) is connected in series between the first voltage node (V1) and the second voltage node (V2) in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node (N2). An output line (Vout) is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.