发明公开
- 专利标题: SAMPLE AND HOLD CIRCUITS
- 专利标题(中): 采样保持电路
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申请号: EP05787013.1申请日: 2005-09-28
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公开(公告)号: EP1803130A1公开(公告)日: 2007-07-04
- 发明人: RODRIGUEZ-VILLEGAS, Esther, O., Flat 23, , CORBISHLEY, Philip, George
- 申请人: Imperial Innovations Limited
- 申请人地址: Level 12 Electrical and Electronic Engineering Building Imperial College London SW7 2AZ GB
- 专利权人: Imperial Innovations Limited
- 当前专利权人: Imperial Innovations Limited
- 当前专利权人地址: Level 12 Electrical and Electronic Engineering Building Imperial College London SW7 2AZ GB
- 代理机构: Camp, Ronald
- 优先权: GB0421535 20040928
- 国际公布: WO2006035230 20060406
- 主分类号: G11C27/02
- IPC分类号: G11C27/02 ; G06G7/00 ; H03M1/00 ; H03H15/02
摘要:
The voltage produced by an input current (in) is sampled (S1, S2, S3) and stored on the gate (46) of a Fet (T1). The stored gate voltage allows the FET to function as the reference current source of a current mirror (T2, T3) which generates an output current (iout) proportional to the sampled input current. The current mirror uses dual gate floating gate FETS (T2, T3) whose mirroring ratio can be finely adjusted by adjusting the bias voltages (V1, V2) applied to their auxiliary gate electrodes (425, 435).
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