There is provided a digital fractional phase detector (200) comprising a first input to receive an oscillator clock signal (CKV) and a second input to receive a frequency reference clock signal (FREF). A time-to-digital converter TDC (201) is coupled to said first input and said second input, said TDC producing a signal indicative of timing difference between said oscillator clock signal and said frequency clock signal. A normalizer (NORM) is coupled to said TDC (201), said normalizer producing an output, wherein said output is normalized to a period of said oscillator clock signal. Also provided is a method of generating a fractional phase error signal whereby a timing difference between an oscillator clock signal and a frequency reference clock signal is obtained, and then normalizing said timing difference to a period of said oscillator clock signal.