发明公开
- 专利标题: VERTICAL-CHANNEL JUNCTION FIELD-EFFECT TRANSISTORS HAVING BURIED GATES AND METHODS OF MAKING
- 专利标题(中): 埋门和方法垂直渠道壁垒场效应晶体管
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申请号: EP05858324申请日: 2005-11-16
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公开(公告)号: EP1913640A4公开(公告)日: 2009-09-02
- 发明人: CHENG LIN , MAZZOLA MICHAEL S
- 申请人: SEMISOUTH LAB INC , UNIV MISSISSIPPI
- 专利权人: SEMISOUTH LAB INC,UNIV MISSISSIPPI
- 当前专利权人: SEMISOUTH LAB INC,UNIV MISSISSIPPI
- 优先权: US19829805 2005-08-08
- 主分类号: H01L29/74
- IPC分类号: H01L29/74 ; H01L29/80 ; H01L31/111 ; H01L31/112
摘要:
Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include expitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
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