发明公开
- 专利标题: AN INTERCONNECT IMPLEMENTING INTERNAL CONTROLS
- 专利标题(中): 内部控制实施的连接器
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申请号: EP08780967.9申请日: 2008-06-25
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公开(公告)号: EP2160762A1公开(公告)日: 2010-03-10
- 发明人: WINGARD, Drew E. , CHOU, Chien-Chun , HAMILTON, Stephen W. , SWARBRICK, Ian Andrew , VAKILOTOJAR, Vida
- 申请人: Sonics, INC. , Wingard, Drew E. , Chou, Chien-Chun , Hamilton, Stephen W. , Swarbrick, Ian Andrew , Vakilotojar, Vida
- 申请人地址: 890 N. Mccarthy Boulevard, Suite 200 Milpitas, CA 95035 US
- 专利权人: Sonics, INC.,Wingard, Drew E.,Chou, Chien-Chun,Hamilton, Stephen W.,Swarbrick, Ian Andrew,Vakilotojar, Vida
- 当前专利权人: Sonics, INC.,Wingard, Drew E.,Chou, Chien-Chun,Hamilton, Stephen W.,Swarbrick, Ian Andrew,Vakilotojar, Vida
- 当前专利权人地址: 890 N. Mccarthy Boulevard, Suite 200 Milpitas, CA 95035 US
- 代理机构: Bartle, Robin Jonathan
- 优先权: US946096P 20070625; US144883 20080624
- 国际公布: WO2009002998 20081231
- 主分类号: H01L25/00
- IPC分类号: H01L25/00
摘要:
A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
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