公开(公告)号：EP2160762A1

公开(公告)日：2010-03-10

申请号：EP08780967.9

申请日：2008-06-25

申请人： Sonics, INC. ,  Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

发明人： WINGARD, Drew E. ,  CHOU, Chien-Chun ,  HAMILTON, Stephen W. ,  SWARBRICK, Ian Andrew ,  VAKILOTOJAR, Vida

IPC分类号： H01L25/00

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

公开(公告)号：EP2216722A2

公开(公告)日：2010-08-11

申请号：EP10157427.5

申请日：2008-06-25

申请人： Sonics, INC. ,  Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

发明人： WINGARD, Drew E. ,  CHOU, Chein-Chun ,  HAMILTON, Stephen W. ,  SWARBRICK, Ian Andrew ,  VAKILOTOJAR, Vida

IPC分类号： G06F12/06

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

公开(公告)号：EP2216722B1

公开(公告)日：2019-06-19

申请号：EP10157427.5

申请日：2008-06-25

申请人： Sonics, INC. ,  Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

发明人： WINGARD, Drew E. ,  CHOU, Chein-Chun ,  HAMILTON, Stephen W. ,  SWARBRICK, Ian Andrew ,  VAKILOTOJAR, Vida

IPC分类号： G06F12/06 ,  G06F15/173

公开(公告)号：EP2413355A1

公开(公告)日：2012-02-01

申请号：EP11186954.1

申请日：2008-06-25

申请人： Sonics, INC. ,  Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

发明人： Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

IPC分类号： H01L25/00 ,  G06F13/16

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.

摘要翻译： 一种方法，装置和系统中，其基因反弹涉及在具有互连集成电路。 用于互连的流动控制逻辑适用的流量控制分割协议以允许从各启动器线程和/或每个引发剂每天流交易是优秀到多个通道在一个单一的聚合目标一次，并且因此多个单独的目标之内对总 针对一次。 将合并的流控制逻辑和流量控制协议允许该互连来管理在聚合目标从在Sametime同一线程或标签同时请求到多个通道英寸

公开(公告)号：EP2216722A3

公开(公告)日：2012-11-21

申请号：EP10157427.5

申请日：2008-06-25

申请人： Sonics, INC. ,  Wingard, Drew E. ,  Chou, Chien-Chun ,  Hamilton, Stephen W. ,  Swarbrick, Ian Andrew ,  Vakilotojar, Vida

发明人： WINGARD, Drew E. ,  CHOU, Chein-Chun ,  HAMILTON, Stephen W. ,  SWARBRICK, Ian Andrew ,  VAKILOTOJAR, Vida

IPC分类号： G06F12/06 ,  G06F15/173

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

摘要翻译： 一种方法，装置和系统中，其基因反弹涉及互连路由交易到目标IP内核，包括两个或多个通道组成的第一聚合目标。 所述两个或多个信道来填充分配给第一总目标地址空间，并且显示为单个目标到始发者的IP内核。 互连器具斩波逻辑，在单个交易从第一发起者IP核为地址序列跨越从第一通道到所述第一集合目标内的第二通道成两个或更多突发交易的信道地址边界劈。 第一切碎突发事务被切碎以适合第一信道和第二切碎突发事务被切碎以配合第二通道的地址范围内的地址范围内。

公开(公告)号：EP2160762A4

公开(公告)日：2011-01-26

申请号：EP08780967

申请日：2008-06-25

申请人： SONICS INC ,  WINGARD DREW E ,  CHOU CHIEN CHUN ,  HAMILTON STEPHEN W ,  SWARBRICK IAN ANDREW ,  VAKILOTOJAR VIDA

发明人： WINGARD DREW E ,  CHOU CHIEN-CHUN ,  HAMILTON STEPHEN W ,  SWARBRICK IAN ANDREW ,  VAKILOTOJAR VIDA

IPC分类号： H01L25/00

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。 两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，其中第一起始IP核的地址序列与第一聚合目标中的第一信道到第二信道的信道地址边界跨越到两个或多个突发事务。 第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切碎突发事务被切碎以适合于第二通道的地址边界内。