发明公开
EP2550659A1 LOW-POWER 5T SRAM WITH IMPROVED STABILITY AND REDUCED BITCELL SIZE
审中-公开
稳定性增加，减少BITZELLENGRÖSSE精力不济IT SRAM
- 专利标题： LOW-POWER 5T SRAM WITH IMPROVED STABILITY AND REDUCED BITCELL SIZE
- 专利标题（中）： 稳定性增加，减少BITZELLENGRÖSSE精力不济IT SRAM
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申请号： EP11713411.4申请日： 2011-03-25
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公开(公告)号： EP2550659A1公开(公告)日： 2013-01-30
- 发明人: JUNG, Seong-Ook , PARK, Hyunkook , SONG, Seung-Chul , ABU-RAHMA, Mohamed Hassan , GE, Lixin , WANG, Zhongze , HAN, Beom-Mo
- 申请人： Qualcomm Incorporated
- 申请人地址： International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 专利权人： Qualcomm Incorporated
- 当前专利权人： Qualcomm Incorporated
- 当前专利权人地址： International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 代理机构： Dunlop, Hugh Christopher
- 优先权： US731668 20100325
- 国际公布： WO2011119941 20110929
- 主分类号： G11C11/412
- IPC分类号： G11C11/412
摘要：
A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
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