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    COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR
    1.
    发明公开
    COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR 审中-公开
    线（电容器）电容补偿后端

    公开(公告)号：EP2959507A1

    公开(公告)日：2015-12-30

    申请号：EP14707282.1

    申请日：2014-02-11

    申请人： Qualcomm Incorporated

    发明人： ZHU, John J. ,  YANG, Bin ,  CHIDAMBARAM, Pr ,  GE, Lixin ,  CHOI, Jihong

    IPC分类号： H01L23/522

    CPC分类号： H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

    摘要翻译： 互补线后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连堆叠的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连堆叠的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 另外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

    STABLE SRAM BITCELL DESIGN UTILIZING INDEPENDENT GATE FINFET
    2.
    发明公开
    STABLE SRAM BITCELL DESIGN UTILIZING INDEPENDENT GATE FINFET 有权
    设计一个稳定的SRAM单元采用独立栅极FET

    公开(公告)号：EP2636039A1

    公开(公告)日：2013-09-11

    申请号：EP11787967.6

    申请日：2011-11-04

    申请人： Qualcomm Incorporated

    发明人： JUNG, Seong-Ook ,  KANG, Mingu ,  PARK, Hyunkook ,  SONG, Seung-Chul ,  ABU-RAHAMA, Mohamed ,  HAN, Beom-Mo ,  GE, Lixin ,  WANG, Zhongze

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10T29/49117

    摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

    STABLE SRAM BITCELL DESIGN UTILIZING INDEPENDENT GATE FINFET
    7.
    发明授权
    STABLE SRAM BITCELL DESIGN UTILIZING INDEPENDENT GATE FINFET 有权
    设计一个稳定的SRAM单元采用独立栅极FET

    公开(公告)号：EP2636039B1

    公开(公告)日：2015-01-14

    申请号：EP11787967.6

    申请日：2011-11-04

    申请人： Qualcomm Incorporated

    发明人： JUNG, Seong-Ook ,  KANG, Mingu ,  PARK, Hyunkook ,  SONG, Seung-Chul ,  ABU-RAHAMA, Mohamed ,  HAN, Beom-Mo ,  GE, Lixin ,  WANG, Zhongze

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10T29/49117

    摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.